[8ac5fe7] | 1 | #
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[df4ed85] | 2 | # Copyright (c) 2005 Jakub Jermar
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[8ac5fe7] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | /**
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[fd85ae5] | 30 | * @file
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| 31 | * @brief This file contains kernel trap table.
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[8ac5fe7] | 32 | */
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[7614565] | 33 |
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| 34 | .register %g2, #scratch
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| 35 | .register %g3, #scratch
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| 36 |
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[8ac5fe7] | 37 | .text
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| 38 |
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[a52e2f4] | 39 | #include <abi/asmtool.h>
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[49b6d32] | 40 | #include <arch/trap/trap_table.h>
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| 41 | #include <arch/trap/regwin.h>
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[5b1ced0] | 42 | #include <arch/trap/interrupt.h>
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[feb5915] | 43 | #include <arch/trap/exception.h>
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[9314ee1] | 44 | #include <arch/trap/syscall.h>
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[008029d] | 45 | #include <arch/trap/mmu.h>
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[ed166f7] | 46 | #include <arch/mm/mmu.h>
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[ee454eb] | 47 | #include <arch/mm/page.h>
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[feb5915] | 48 | #include <arch/stack.h>
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[f47fd19] | 49 | #include <arch/regdef.h>
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[8ac5fe7] | 50 |
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| 51 | #define TABLE_SIZE TRAP_TABLE_SIZE
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| 52 | #define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE
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| 53 |
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| 54 | /*
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[c43fa55] | 55 | * Kernel trap table.
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[8ac5fe7] | 56 | */
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| 57 | .align TABLE_SIZE
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[a52e2f4] | 58 | SYMBOL(trap_table)
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[8ac5fe7] | 59 |
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[feb5915] | 60 | /* TT = 0x08, TL = 0, instruction_access_exception */
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| 61 | .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
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[a52e2f4] | 62 | SYMBOL(instruction_access_exception_tl0)
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[e2bf639] | 63 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
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[ec443d5] | 64 | mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
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[d70ebffe] | 65 | clr %g5
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[1b20da0] | 66 | PREEMPTIBLE_HANDLER exc_dispatch
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[e2bf639] | 67 |
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| 68 | /* TT = 0x0a, TL = 0, instruction_access_error */
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| 69 | .org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE
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[a52e2f4] | 70 | SYMBOL(instruction_access_error_tl0)
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[ec443d5] | 71 | mov TT_INSTRUCTION_ACCESS_ERROR, %g2
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[d70ebffe] | 72 | clr %g5
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[1b20da0] | 73 | PREEMPTIBLE_HANDLER exc_dispatch
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[feb5915] | 74 |
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[7cb53f62] | 75 | /* TT = 0x10, TL = 0, illegal_instruction */
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| 76 | .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
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[a52e2f4] | 77 | SYMBOL(illegal_instruction_tl0)
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[ec443d5] | 78 | mov TT_ILLEGAL_INSTRUCTION, %g2
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[d70ebffe] | 79 | clr %g5
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[1b20da0] | 80 | PREEMPTIBLE_HANDLER exc_dispatch
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[e2bf639] | 81 |
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| 82 | /* TT = 0x11, TL = 0, privileged_opcode */
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| 83 | .org trap_table + TT_PRIVILEGED_OPCODE*ENTRY_SIZE
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[a52e2f4] | 84 | SYMBOL(privileged_opcode_tl0)
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[ec443d5] | 85 | mov TT_PRIVILEGED_OPCODE, %g2
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[d70ebffe] | 86 | clr %g5
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[1b20da0] | 87 | PREEMPTIBLE_HANDLER exc_dispatch
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[7cb53f62] | 88 |
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[34d9469e] | 89 | /* TT = 0x12, TL = 0, unimplemented_LDD */
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| 90 | .org trap_table + TT_UNIMPLEMENTED_LDD*ENTRY_SIZE
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[a52e2f4] | 91 | SYMBOL(unimplemented_LDD_tl0)
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[ec443d5] | 92 | mov TT_UNIMPLEMENTED_LDD, %g2
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[d70ebffe] | 93 | clr %g5
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[1b20da0] | 94 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 95 |
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| 96 | /* TT = 0x13, TL = 0, unimplemented_STD */
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| 97 | .org trap_table + TT_UNIMPLEMENTED_STD*ENTRY_SIZE
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[a52e2f4] | 98 | SYMBOL(unimplemented_STD_tl0)
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[ec443d5] | 99 | mov TT_UNIMPLEMENTED_STD, %g2
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[d70ebffe] | 100 | clr %g5
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[ec443d5] | 101 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 102 |
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[6eabb6e6] | 103 | /* TT = 0x20, TL = 0, fb_disabled handler */
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| 104 | .org trap_table + TT_FP_DISABLED*ENTRY_SIZE
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[a52e2f4] | 105 | SYMBOL(fp_disabled_tl0)
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[ec443d5] | 106 | mov TT_FP_DISABLED, %g2
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[d70ebffe] | 107 | clr %g5
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[1b20da0] | 108 | PREEMPTIBLE_HANDLER exc_dispatch
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[6eabb6e6] | 109 |
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[34d9469e] | 110 | /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
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| 111 | .org trap_table + TT_FP_EXCEPTION_IEEE_754*ENTRY_SIZE
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[a52e2f4] | 112 | SYMBOL(fp_exception_ieee_754_tl0)
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[ec443d5] | 113 | mov TT_FP_EXCEPTION_IEEE_754, %g2
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[d70ebffe] | 114 | clr %g5
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[ec443d5] | 115 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 116 |
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| 117 | /* TT = 0x22, TL = 0, fb_exception_other handler */
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| 118 | .org trap_table + TT_FP_EXCEPTION_OTHER*ENTRY_SIZE
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[a52e2f4] | 119 | SYMBOL(fp_exception_other_tl0)
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[ec443d5] | 120 | mov TT_FP_EXCEPTION_OTHER, %g2
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[d70ebffe] | 121 | clr %g5
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[ec443d5] | 122 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 123 |
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| 124 | /* TT = 0x23, TL = 0, tag_overflow */
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| 125 | .org trap_table + TT_TAG_OVERFLOW*ENTRY_SIZE
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[a52e2f4] | 126 | SYMBOL(tag_overflow_tl0)
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[ec443d5] | 127 | mov TT_TAG_OVERFLOW, %g2
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[d70ebffe] | 128 | clr %g5
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[ec443d5] | 129 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 130 |
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[5b1ced0] | 131 | /* TT = 0x24, TL = 0, clean_window handler */
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[c43fa55] | 132 | .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
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[a52e2f4] | 133 | SYMBOL(clean_window_tl0)
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[49b6d32] | 134 | CLEAN_WINDOW_HANDLER
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[8ac5fe7] | 135 |
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[e2bf639] | 136 | /* TT = 0x28, TL = 0, division_by_zero */
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| 137 | .org trap_table + TT_DIVISION_BY_ZERO*ENTRY_SIZE
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[a52e2f4] | 138 | SYMBOL(division_by_zero_tl0)
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[ec443d5] | 139 | mov TT_DIVISION_BY_ZERO, %g2
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[d70ebffe] | 140 | clr %g5
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[ec443d5] | 141 | PREEMPTIBLE_HANDLER exc_dispatch
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[e2bf639] | 142 |
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| 143 | /* TT = 0x30, TL = 0, data_access_exception */
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| 144 | .org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE
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[a52e2f4] | 145 | SYMBOL(data_access_exception_tl0)
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[e2bf639] | 146 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
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[ec443d5] | 147 | mov TT_DATA_ACCESS_EXCEPTION, %g2
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[d70ebffe] | 148 | clr %g5
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[ec443d5] | 149 | PREEMPTIBLE_HANDLER exc_dispatch
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[e2bf639] | 150 |
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[97f1691] | 151 | /* TT = 0x32, TL = 0, data_access_error */
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| 152 | .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
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[a52e2f4] | 153 | SYMBOL(data_access_error_tl0)
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[ec443d5] | 154 | mov TT_DATA_ACCESS_ERROR, %g2
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[d70ebffe] | 155 | clr %g5
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[ec443d5] | 156 | PREEMPTIBLE_HANDLER exc_dispatch
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[97f1691] | 157 |
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[feb5915] | 158 | /* TT = 0x34, TL = 0, mem_address_not_aligned */
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| 159 | .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
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[a52e2f4] | 160 | SYMBOL(mem_address_not_aligned_tl0)
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[ec443d5] | 161 | mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
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[d70ebffe] | 162 | clr %g5
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[ec443d5] | 163 | PREEMPTIBLE_HANDLER exc_dispatch
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[e2bf639] | 164 |
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[34d9469e] | 165 | /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
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| 166 | .org trap_table + TT_LDDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
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[a52e2f4] | 167 | SYMBOL(LDDF_mem_address_not_aligned_tl0)
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[ec443d5] | 168 | mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
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[d70ebffe] | 169 | clr %g5
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[1b20da0] | 170 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 171 |
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| 172 | /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
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| 173 | .org trap_table + TT_STDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
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[a52e2f4] | 174 | SYMBOL(STDF_mem_address_not_aligned_tl0)
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[ec443d5] | 175 | mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
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[d70ebffe] | 176 | clr %g5
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[ec443d5] | 177 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 178 |
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| 179 | /* TT = 0x37, TL = 0, privileged_action */
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[e2bf639] | 180 | .org trap_table + TT_PRIVILEGED_ACTION*ENTRY_SIZE
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[a52e2f4] | 181 | SYMBOL(privileged_action_tl0)
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[ec443d5] | 182 | mov TT_PRIVILEGED_ACTION, %g2
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[d70ebffe] | 183 | clr %g5
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[ec443d5] | 184 | PREEMPTIBLE_HANDLER exc_dispatch
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[feb5915] | 185 |
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[34d9469e] | 186 | /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
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| 187 | .org trap_table + TT_LDQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
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[a52e2f4] | 188 | SYMBOL(LDQF_mem_address_not_aligned_tl0)
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[ec443d5] | 189 | mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
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[d70ebffe] | 190 | clr %g5
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[ec443d5] | 191 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 192 |
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| 193 | /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
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| 194 | .org trap_table + TT_STQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
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[a52e2f4] | 195 | SYMBOL(STQF_mem_address_not_aligned_tl0)
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[ec443d5] | 196 | mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
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[d70ebffe] | 197 | clr %g5
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[ec443d5] | 198 | PREEMPTIBLE_HANDLER exc_dispatch
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[34d9469e] | 199 |
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[39494010] | 200 | /* TT = 0x41, TL = 0, interrupt_level_1 handler */
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| 201 | .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
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[a52e2f4] | 202 | SYMBOL(interrupt_level_1_handler_tl0)
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[ec443d5] | 203 | mov TT_INTERRUPT_LEVEL_1, %g2
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[d70ebffe] | 204 | clr %g5
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[ec443d5] | 205 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 206 |
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| 207 | /* TT = 0x42, TL = 0, interrupt_level_2 handler */
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| 208 | .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
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[a52e2f4] | 209 | SYMBOL(interrupt_level_2_handler_tl0)
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[ec443d5] | 210 | mov TT_INTERRUPT_LEVEL_2, %g2
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[d70ebffe] | 211 | clr %g5
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[ec443d5] | 212 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 213 |
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| 214 | /* TT = 0x43, TL = 0, interrupt_level_3 handler */
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| 215 | .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
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[a52e2f4] | 216 | SYMBOL(interrupt_level_3_handler_tl0)
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[ec443d5] | 217 | mov TT_INTERRUPT_LEVEL_3, %g2
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[d70ebffe] | 218 | clr %g5
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[ec443d5] | 219 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 220 |
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| 221 | /* TT = 0x44, TL = 0, interrupt_level_4 handler */
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| 222 | .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
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[a52e2f4] | 223 | SYMBOL(interrupt_level_4_handler_tl0)
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[ec443d5] | 224 | mov TT_INTERRUPT_LEVEL_4, %g2
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[d70ebffe] | 225 | clr %g5
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[ec443d5] | 226 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 227 |
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| 228 | /* TT = 0x45, TL = 0, interrupt_level_5 handler */
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| 229 | .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
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[a52e2f4] | 230 | SYMBOL(interrupt_level_5_handler_tl0)
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[ec443d5] | 231 | mov TT_INTERRUPT_LEVEL_5, %g2
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[d70ebffe] | 232 | clr %g5
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[ec443d5] | 233 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 234 |
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| 235 | /* TT = 0x46, TL = 0, interrupt_level_6 handler */
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| 236 | .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
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[a52e2f4] | 237 | SYMBOL(interrupt_level_6_handler_tl0)
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[ec443d5] | 238 | mov TT_INTERRUPT_LEVEL_6, %g2
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[d70ebffe] | 239 | clr %g5
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[ec443d5] | 240 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 241 |
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| 242 | /* TT = 0x47, TL = 0, interrupt_level_7 handler */
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| 243 | .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
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[a52e2f4] | 244 | SYMBOL(interrupt_level_7_handler_tl0)
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[ec443d5] | 245 | mov TT_INTERRUPT_LEVEL_7, %g2
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[d70ebffe] | 246 | clr %g5
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[ec443d5] | 247 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 248 |
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| 249 | /* TT = 0x48, TL = 0, interrupt_level_8 handler */
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| 250 | .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
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[a52e2f4] | 251 | SYMBOL(interrupt_level_8_handler_tl0)
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[ec443d5] | 252 | mov TT_INTERRUPT_LEVEL_8, %g2
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[d70ebffe] | 253 | clr %g5
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[ec443d5] | 254 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 255 |
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| 256 | /* TT = 0x49, TL = 0, interrupt_level_9 handler */
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| 257 | .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
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[a52e2f4] | 258 | SYMBOL(interrupt_level_9_handler_tl0)
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[ec443d5] | 259 | mov TT_INTERRUPT_LEVEL_9, %g2
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[d70ebffe] | 260 | clr %g5
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[ec443d5] | 261 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 262 |
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| 263 | /* TT = 0x4a, TL = 0, interrupt_level_10 handler */
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| 264 | .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
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[a52e2f4] | 265 | SYMBOL(interrupt_level_10_handler_tl0)
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[ec443d5] | 266 | mov TT_INTERRUPT_LEVEL_10, %g2
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[d70ebffe] | 267 | clr %g5
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[ec443d5] | 268 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 269 |
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| 270 | /* TT = 0x4b, TL = 0, interrupt_level_11 handler */
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| 271 | .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
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[a52e2f4] | 272 | SYMBOL(interrupt_level_11_handler_tl0)
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[ec443d5] | 273 | mov TT_INTERRUPT_LEVEL_11, %g2
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[d70ebffe] | 274 | clr %g5
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[ec443d5] | 275 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 276 |
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| 277 | /* TT = 0x4c, TL = 0, interrupt_level_12 handler */
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| 278 | .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
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[a52e2f4] | 279 | SYMBOL(interrupt_level_12_handler_tl0)
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[ec443d5] | 280 | mov TT_INTERRUPT_LEVEL_12, %g2
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[d70ebffe] | 281 | clr %g5
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[ec443d5] | 282 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 283 |
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| 284 | /* TT = 0x4d, TL = 0, interrupt_level_13 handler */
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| 285 | .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
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[a52e2f4] | 286 | SYMBOL(interrupt_level_13_handler_tl0)
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[ec443d5] | 287 | mov TT_INTERRUPT_LEVEL_13, %g2
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[d70ebffe] | 288 | clr %g5
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[ec443d5] | 289 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 290 |
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| 291 | /* TT = 0x4e, TL = 0, interrupt_level_14 handler */
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| 292 | .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
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[a52e2f4] | 293 | SYMBOL(interrupt_level_14_handler_tl0)
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[ec443d5] | 294 | mov TT_INTERRUPT_LEVEL_14, %g2
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[d70ebffe] | 295 | clr %g5
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[ec443d5] | 296 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 297 |
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| 298 | /* TT = 0x4f, TL = 0, interrupt_level_15 handler */
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| 299 | .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
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[a52e2f4] | 300 | SYMBOL(interrupt_level_15_handler_tl0)
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[ec443d5] | 301 | mov TT_INTERRUPT_LEVEL_15, %g2
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[d70ebffe] | 302 | clr %g5
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[ec443d5] | 303 | PREEMPTIBLE_HANDLER exc_dispatch
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[39494010] | 304 |
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[5b1ced0] | 305 | /* TT = 0x60, TL = 0, interrupt_vector_trap handler */
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| 306 | .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
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[a52e2f4] | 307 | SYMBOL(interrupt_vector_trap_handler_tl0)
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[ec443d5] | 308 | mov TT_INTERRUPT_VECTOR_TRAP, %g2
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[d70ebffe] | 309 | clr %g5
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[ec443d5] | 310 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[5b1ced0] | 311 |
|
---|
[008029d] | 312 | /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
|
---|
| 313 | .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
|
---|
[a52e2f4] | 314 | SYMBOL(fast_instruction_access_mmu_miss_handler_tl0)
|
---|
[008029d] | 315 | FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
|
---|
| 316 |
|
---|
| 317 | /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
|
---|
| 318 | .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
|
---|
[a52e2f4] | 319 | SYMBOL(fast_data_access_mmu_miss_handler_tl0)
|
---|
[e2bf639] | 320 | FAST_DATA_ACCESS_MMU_MISS_HANDLER 0
|
---|
[008029d] | 321 |
|
---|
| 322 | /* TT = 0x6c, TL = 0, fast_data_access_protection */
|
---|
| 323 | .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
|
---|
[a52e2f4] | 324 | SYMBOL(fast_data_access_protection_handler_tl0)
|
---|
[e2bf639] | 325 | FAST_DATA_ACCESS_PROTECTION_HANDLER 0
|
---|
[008029d] | 326 |
|
---|
[5b1ced0] | 327 | /* TT = 0x80, TL = 0, spill_0_normal handler */
|
---|
[c43fa55] | 328 | .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
|
---|
[a52e2f4] | 329 | SYMBOL(spill_0_normal_tl0)
|
---|
[a7961271] | 330 | SPILL_NORMAL_HANDLER_KERNEL
|
---|
[49b6d32] | 331 |
|
---|
[e11ae91] | 332 | /* TT = 0x84, TL = 0, spill_1_normal handler */
|
---|
| 333 | .org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE
|
---|
[a52e2f4] | 334 | SYMBOL(spill_1_normal_tl0)
|
---|
[e11ae91] | 335 | SPILL_NORMAL_HANDLER_USERSPACE
|
---|
| 336 |
|
---|
| 337 | /* TT = 0x88, TL = 0, spill_2_normal handler */
|
---|
| 338 | .org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE
|
---|
[a52e2f4] | 339 | SYMBOL(spill_2_normal_tl0)
|
---|
[e11ae91] | 340 | SPILL_TO_USPACE_WINDOW_BUFFER
|
---|
| 341 |
|
---|
[cfa70add] | 342 | /* TT = 0xa0, TL = 0, spill_0_other handler */
|
---|
| 343 | .org trap_table + TT_SPILL_0_OTHER*ENTRY_SIZE
|
---|
[a52e2f4] | 344 | SYMBOL(spill_0_other_tl0)
|
---|
[cfa70add] | 345 | SPILL_TO_USPACE_WINDOW_BUFFER
|
---|
| 346 |
|
---|
[5b1ced0] | 347 | /* TT = 0xc0, TL = 0, fill_0_normal handler */
|
---|
[c43fa55] | 348 | .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
|
---|
[a52e2f4] | 349 | SYMBOL(fill_0_normal_tl0)
|
---|
[a7961271] | 350 | FILL_NORMAL_HANDLER_KERNEL
|
---|
[8ac5fe7] | 351 |
|
---|
[e11ae91] | 352 | /* TT = 0xc4, TL = 0, fill_1_normal handler */
|
---|
| 353 | .org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE
|
---|
[a52e2f4] | 354 | SYMBOL(fill_1_normal_tl0)
|
---|
[e11ae91] | 355 | FILL_NORMAL_HANDLER_USERSPACE
|
---|
| 356 |
|
---|
[3b8fe85] | 357 | /* TT = 0x100 - 0x17f, TL = 0, trap_instruction_0 - trap_instruction_7f */
|
---|
| 358 | .irp cur, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\
|
---|
| 359 | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\
|
---|
| 360 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\
|
---|
| 361 | 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,\
|
---|
| 362 | 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,\
|
---|
| 363 | 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\
|
---|
| 364 | 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,\
|
---|
| 365 | 127
|
---|
| 366 | .org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE
|
---|
[a52e2f4] | 367 | SYMBOL(trap_instruction_\cur\()_tl0)
|
---|
[3b8fe85] | 368 | mov \cur, %g2
|
---|
[d70ebffe] | 369 | ba %xcc, trap_instruction_handler
|
---|
| 370 | clr %g5
|
---|
[3b8fe85] | 371 | .endr
|
---|
[d93a1c5a] | 372 |
|
---|
[8ac5fe7] | 373 | /*
|
---|
[5b1ced0] | 374 | * Handlers for TL>0.
|
---|
[8ac5fe7] | 375 | */
|
---|
| 376 |
|
---|
[feb5915] | 377 | /* TT = 0x08, TL > 0, instruction_access_exception */
|
---|
| 378 | .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 379 | SYMBOL(instruction_access_exception_tl1)
|
---|
[e2bf639] | 380 | wrpr %g0, 1, %tl
|
---|
| 381 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
|
---|
[ec443d5] | 382 | mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
|
---|
[d70ebffe] | 383 | clr %g5
|
---|
[1b20da0] | 384 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[e2bf639] | 385 |
|
---|
| 386 | /* TT = 0x0a, TL > 0, instruction_access_error */
|
---|
| 387 | .org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 388 | SYMBOL(instruction_access_error_tl1)
|
---|
[e2bf639] | 389 | wrpr %g0, 1, %tl
|
---|
[ec443d5] | 390 | mov TT_INSTRUCTION_ACCESS_ERROR, %g2
|
---|
[d70ebffe] | 391 | clr %g5
|
---|
[ec443d5] | 392 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[feb5915] | 393 |
|
---|
[7cb53f62] | 394 | /* TT = 0x10, TL > 0, illegal_instruction */
|
---|
| 395 | .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 396 | SYMBOL(illegal_instruction_tl1)
|
---|
[e2bf639] | 397 | wrpr %g0, 1, %tl
|
---|
[ec443d5] | 398 | mov TT_ILLEGAL_INSTRUCTION, %g2
|
---|
[d70ebffe] | 399 | clr %g5
|
---|
[ec443d5] | 400 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[7cb53f62] | 401 |
|
---|
[5b1ced0] | 402 | /* TT = 0x24, TL > 0, clean_window handler */
|
---|
| 403 | .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 404 | SYMBOL(clean_window_tl1)
|
---|
[5b1ced0] | 405 | CLEAN_WINDOW_HANDLER
|
---|
[8ac5fe7] | 406 |
|
---|
[e2bf639] | 407 | /* TT = 0x28, TL > 0, division_by_zero */
|
---|
| 408 | .org trap_table + (TT_DIVISION_BY_ZERO+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 409 | SYMBOL(division_by_zero_tl1)
|
---|
[e2bf639] | 410 | wrpr %g0, 1, %tl
|
---|
[ec443d5] | 411 | mov TT_DIVISION_BY_ZERO, %g2
|
---|
[d70ebffe] | 412 | clr %g5
|
---|
[ec443d5] | 413 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[e2bf639] | 414 |
|
---|
| 415 | /* TT = 0x30, TL > 0, data_access_exception */
|
---|
| 416 | .org trap_table + (TT_DATA_ACCESS_EXCEPTION+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 417 | SYMBOL(data_access_exception_tl1)
|
---|
[e2bf639] | 418 | wrpr %g0, 1, %tl
|
---|
| 419 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
|
---|
[ec443d5] | 420 | mov TT_DATA_ACCESS_EXCEPTION, %g2
|
---|
[d70ebffe] | 421 | clr %g5
|
---|
[ec443d5] | 422 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[e2bf639] | 423 |
|
---|
[97f1691] | 424 | /* TT = 0x32, TL > 0, data_access_error */
|
---|
| 425 | .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 426 | SYMBOL(data_access_error_tl1)
|
---|
[e2bf639] | 427 | wrpr %g0, 1, %tl
|
---|
[ec443d5] | 428 | mov TT_DATA_ACCESS_ERROR, %g2
|
---|
[d70ebffe] | 429 | clr %g5
|
---|
[ec443d5] | 430 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[97f1691] | 431 |
|
---|
[feb5915] | 432 | /* TT = 0x34, TL > 0, mem_address_not_aligned */
|
---|
| 433 | .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 434 | SYMBOL(mem_address_not_aligned_tl1)
|
---|
[e2bf639] | 435 | wrpr %g0, 1, %tl
|
---|
[ec443d5] | 436 | mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
|
---|
[d70ebffe] | 437 | clr %g5
|
---|
[ec443d5] | 438 | PREEMPTIBLE_HANDLER exc_dispatch
|
---|
[008029d] | 439 |
|
---|
| 440 | /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
|
---|
| 441 | .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 442 | SYMBOL(fast_data_access_mmu_miss_handler_tl1)
|
---|
[e2bf639] | 443 | FAST_DATA_ACCESS_MMU_MISS_HANDLER 1
|
---|
[008029d] | 444 |
|
---|
| 445 | /* TT = 0x6c, TL > 0, fast_data_access_protection */
|
---|
| 446 | .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 447 | SYMBOL(fast_data_access_protection_handler_tl1)
|
---|
[e2bf639] | 448 | FAST_DATA_ACCESS_PROTECTION_HANDLER 1
|
---|
[008029d] | 449 |
|
---|
[5b1ced0] | 450 | /* TT = 0x80, TL > 0, spill_0_normal handler */
|
---|
| 451 | .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 452 | SYMBOL(spill_0_normal_tl1)
|
---|
[a7961271] | 453 | SPILL_NORMAL_HANDLER_KERNEL
|
---|
[8ac5fe7] | 454 |
|
---|
[e11ae91] | 455 | /* TT = 0x88, TL > 0, spill_2_normal handler */
|
---|
| 456 | .org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 457 | SYMBOL(spill_2_normal_tl1)
|
---|
[e11ae91] | 458 | SPILL_TO_USPACE_WINDOW_BUFFER
|
---|
| 459 |
|
---|
| 460 | /* TT = 0xa0, TL > 0, spill_0_other handler */
|
---|
| 461 | .org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 462 | SYMBOL(spill_0_other_tl1)
|
---|
[e11ae91] | 463 | SPILL_TO_USPACE_WINDOW_BUFFER
|
---|
| 464 |
|
---|
[5b1ced0] | 465 | /* TT = 0xc0, TL > 0, fill_0_normal handler */
|
---|
| 466 | .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
|
---|
[a52e2f4] | 467 | SYMBOL(fill_0_normal_tl1)
|
---|
[a7961271] | 468 | FILL_NORMAL_HANDLER_KERNEL
|
---|
[5b1ced0] | 469 |
|
---|
[282f2c9c] | 470 | .align TABLE_SIZE
|
---|
| 471 |
|
---|
| 472 |
|
---|
[9314ee1] | 473 | #define NOT(x) ((x) == 0)
|
---|
[c43fa55] | 474 |
|
---|
[f47fd19] | 475 | /* Preemptible trap handler for TL=1.
|
---|
[feb5915] | 476 | *
|
---|
[f47fd19] | 477 | * This trap handler makes arrangements to make calling of scheduler() from
|
---|
[a7961271] | 478 | * within a trap context possible. It is called from several other trap
|
---|
| 479 | * handlers.
|
---|
[feb5915] | 480 | *
|
---|
[b2e5e25] | 481 | * This function can be entered either with interrupt globals or alternate
|
---|
| 482 | * globals. Memory management trap handlers are obliged to switch to one of
|
---|
| 483 | * those global sets prior to calling this function. Register window management
|
---|
| 484 | * functions are not allowed to modify the alternate global registers.
|
---|
| 485 | *
|
---|
| 486 | * The kernel is designed to work on trap levels 0 - 4. For instance, the
|
---|
| 487 | * following can happen:
|
---|
| 488 | * TL0: kernel thread runs (CANSAVE=0, kernel stack not in DTLB)
|
---|
| 489 | * TL1: preemptible trap handler started after a tick interrupt
|
---|
| 490 | * TL2: preemptible trap handler did SAVE
|
---|
[1b20da0] | 491 | * TL3: spill handler touched the kernel stack
|
---|
[b2e5e25] | 492 | * TL4: hardware or software failure
|
---|
[7614565] | 493 | *
|
---|
| 494 | * Input registers:
|
---|
[05ae7081] | 495 | * %g1 Address of function to call if this is not a syscall.
|
---|
[002e613] | 496 | * %g2 First argument for the function.
|
---|
[d70ebffe] | 497 | * %g5 I/DTLB_TAG_ACCESS register if applicable.
|
---|
[a7961271] | 498 | * %g6 Pre-set as kernel stack base if trap from userspace.
|
---|
[e11ae91] | 499 | * %g7 Pre-set as address of the userspace window buffer.
|
---|
[7614565] | 500 | */
|
---|
[9314ee1] | 501 | .macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall
|
---|
| 502 | .if NOT(\is_syscall)
|
---|
[a7961271] | 503 | rdpr %tstate, %g3
|
---|
[a35b458] | 504 |
|
---|
[ab1ae2d9] | 505 | /*
|
---|
| 506 | * One of the ways this handler can be invoked is after a nested MMU trap from
|
---|
| 507 | * either spill_1_normal or fill_1_normal traps. Both of these traps manipulate
|
---|
| 508 | * the CWP register. We deal with the situation by simulating the MMU trap
|
---|
| 509 | * on TL=1 and restart the respective SAVE or RESTORE instruction once the MMU
|
---|
| 510 | * trap is resolved. However, because we are in the wrong window from the
|
---|
| 511 | * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
|
---|
[1b20da0] | 512 | */
|
---|
[ab1ae2d9] | 513 | and %g3, TSTATE_CWP_MASK, %g4
|
---|
| 514 | wrpr %g4, 0, %cwp ! resynchronize CWP
|
---|
| 515 |
|
---|
[a7961271] | 516 | andcc %g3, TSTATE_PRIV_BIT, %g0 ! if this trap came from the privileged mode...
|
---|
[577b531] | 517 | bnz %xcc, 0f ! ...skip setting of kernel stack and primary context
|
---|
[a7961271] | 518 | nop
|
---|
[9314ee1] | 519 | .endif
|
---|
[d70ebffe] | 520 |
|
---|
[ee454eb] | 521 | /*
|
---|
| 522 | * Normal window spills will go to the userspace window buffer.
|
---|
| 523 | */
|
---|
| 524 | wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(2), %wstate
|
---|
| 525 |
|
---|
[84060e2] | 526 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent unnecessary clean_window exceptions
|
---|
[fd85ae5] | 527 |
|
---|
[a7961271] | 528 | /*
|
---|
| 529 | * Switch to kernel stack. The old stack is
|
---|
| 530 | * automatically saved in the old window's %sp
|
---|
| 531 | * and the new window's %fp.
|
---|
| 532 | */
|
---|
[d70ebffe] | 533 | save %g6, -ISTATE_SIZE, %sp
|
---|
[a7961271] | 534 |
|
---|
[9314ee1] | 535 | .if \is_syscall
|
---|
| 536 | /*
|
---|
| 537 | * Copy arguments for the syscall to the new window.
|
---|
| 538 | */
|
---|
[05ae7081] | 539 | mov %i0, %o0
|
---|
| 540 | mov %i1, %o1
|
---|
| 541 | mov %i2, %o2
|
---|
| 542 | mov %i3, %o3
|
---|
| 543 | mov %i4, %o4
|
---|
| 544 | mov %i5, %o5
|
---|
[9314ee1] | 545 | .endif
|
---|
| 546 |
|
---|
[a7961271] | 547 | /*
|
---|
[cfa70add] | 548 | * Mark the CANRESTORE windows as OTHER windows.
|
---|
[a7961271] | 549 | */
|
---|
[cfa70add] | 550 | rdpr %canrestore, %l0
|
---|
[a7961271] | 551 | wrpr %l0, %otherwin
|
---|
[cfa70add] | 552 | wrpr %g0, %canrestore
|
---|
[a7961271] | 553 |
|
---|
| 554 | /*
|
---|
| 555 | * Switch to primary context 0.
|
---|
| 556 | */
|
---|
| 557 | mov VA_PRIMARY_CONTEXT_REG, %l0
|
---|
[ed166f7] | 558 | stxa %g0, [%l0] ASI_DMMU
|
---|
| 559 | rd %pc, %l0
|
---|
| 560 | flush %l0
|
---|
[a7961271] | 561 |
|
---|
[9314ee1] | 562 | .if NOT(\is_syscall)
|
---|
[40239b9] | 563 | ba,a %xcc, 1f
|
---|
[a7961271] | 564 | 0:
|
---|
[d70ebffe] | 565 | save %sp, -ISTATE_SIZE, %sp
|
---|
[a7961271] | 566 |
|
---|
[feb5915] | 567 | /*
|
---|
[1b20da0] | 568 | * At this moment, we are using the kernel stack
|
---|
[a7961271] | 569 | * and have successfully allocated a register window.
|
---|
| 570 | */
|
---|
| 571 | 1:
|
---|
[9314ee1] | 572 | .endif
|
---|
[ee454eb] | 573 | /*
|
---|
| 574 | * Other window spills will go to the userspace window buffer
|
---|
| 575 | * and normal spills will go to the kernel stack.
|
---|
| 576 | */
|
---|
| 577 | wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
|
---|
[a35b458] | 578 |
|
---|
[a7961271] | 579 | /*
|
---|
| 580 | * Copy arguments.
|
---|
| 581 | */
|
---|
| 582 | mov %g1, %l0
|
---|
[05ae7081] | 583 | .if NOT(\is_syscall)
|
---|
[a7961271] | 584 | mov %g2, %o0
|
---|
[05ae7081] | 585 | .else
|
---|
| 586 | ! store the syscall number on the stack as 7th argument
|
---|
[1b20da0] | 587 | stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
|
---|
[05ae7081] | 588 | .endif
|
---|
[a7961271] | 589 |
|
---|
| 590 | /*
|
---|
[d70ebffe] | 591 | * Save TSTATE, TPC, TNPC and I/DTLB_TAG_ACCESS aside.
|
---|
[feb5915] | 592 | */
|
---|
| 593 | rdpr %tstate, %g1
|
---|
| 594 | rdpr %tpc, %g2
|
---|
| 595 | rdpr %tnpc, %g3
|
---|
[e4398200] | 596 | rd %y, %g4
|
---|
[feb5915] | 597 |
|
---|
[d70ebffe] | 598 | stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
|
---|
| 599 | stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
|
---|
| 600 | stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
|
---|
| 601 | stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
|
---|
[7ba7c6d] | 602 |
|
---|
| 603 | /*
|
---|
| 604 | * Save the Y register.
|
---|
| 605 | */
|
---|
[d70ebffe] | 606 | stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
|
---|
[a35b458] | 607 |
|
---|
[feb5915] | 608 | wrpr %g0, 0, %tl
|
---|
[6eabb6e6] | 609 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
|
---|
[7614565] | 610 | SAVE_GLOBALS
|
---|
[a35b458] | 611 |
|
---|
[05ae7081] | 612 | .if NOT(\is_syscall)
|
---|
[feb5915] | 613 | /*
|
---|
[a7961271] | 614 | * Call the higher-level handler and pass istate as second parameter.
|
---|
[feb5915] | 615 | */
|
---|
[7614565] | 616 | call %l0
|
---|
[d70ebffe] | 617 | add %sp, STACK_BIAS, %o1
|
---|
[05ae7081] | 618 | .else
|
---|
[9314ee1] | 619 | /*
|
---|
[b755225] | 620 | * Call the higher-level syscall handler and enable interrupts.
|
---|
[9314ee1] | 621 | */
|
---|
[05ae7081] | 622 | call syscall_handler
|
---|
[b755225] | 623 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT | PSTATE_IE_BIT, %pstate
|
---|
[05ae7081] | 624 | mov %o0, %i0 ! copy the value returned by the syscall
|
---|
[9314ee1] | 625 | .endif
|
---|
| 626 |
|
---|
[7614565] | 627 | RESTORE_GLOBALS
|
---|
[6eabb6e6] | 628 | rdpr %pstate, %l1 ! we must preserve the PEF bit
|
---|
[a7961271] | 629 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
|
---|
| 630 | wrpr %g0, 1, %tl
|
---|
[a35b458] | 631 |
|
---|
[feb5915] | 632 | /*
|
---|
[a7961271] | 633 | * Read TSTATE, TPC and TNPC from saved copy.
|
---|
[feb5915] | 634 | */
|
---|
[d70ebffe] | 635 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
|
---|
| 636 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
|
---|
| 637 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
|
---|
[a7961271] | 638 |
|
---|
[6eabb6e6] | 639 | /*
|
---|
| 640 | * Copy PSTATE.PEF to the in-register copy of TSTATE.
|
---|
| 641 | */
|
---|
| 642 | and %l1, PSTATE_PEF_BIT, %l1
|
---|
| 643 | sllx %l1, TSTATE_PSTATE_SHIFT, %l1
|
---|
| 644 | sethi %hi(TSTATE_PEF_BIT), %g4
|
---|
| 645 | andn %g1, %g4, %g1
|
---|
| 646 | or %g1, %l1, %g1
|
---|
| 647 |
|
---|
[feb5915] | 648 | /*
|
---|
[a7961271] | 649 | * Restore TSTATE, TPC and TNPC from saved copies.
|
---|
[feb5915] | 650 | */
|
---|
[a7961271] | 651 | wrpr %g1, 0, %tstate
|
---|
| 652 | wrpr %g2, 0, %tpc
|
---|
| 653 | wrpr %g3, 0, %tnpc
|
---|
| 654 |
|
---|
[e4398200] | 655 | /*
|
---|
| 656 | * Restore Y.
|
---|
| 657 | */
|
---|
[d70ebffe] | 658 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
|
---|
[e4398200] | 659 | wr %g4, %y
|
---|
[6eabb6e6] | 660 |
|
---|
[feb5915] | 661 | /*
|
---|
[a7961271] | 662 | * If OTHERWIN is zero, then all the userspace windows have been
|
---|
[cfa70add] | 663 | * spilled to kernel memory (i.e. register window buffer). Moreover,
|
---|
| 664 | * if the scheduler was called in the meantime, all valid windows
|
---|
[245e8399] | 665 | * belonging to other threads were spilled by context_save().
|
---|
[cfa70add] | 666 | * If OTHERWIN is non-zero, then some userspace windows are still
|
---|
[a7961271] | 667 | * valid. Others might have been spilled. However, the CWP pointer
|
---|
| 668 | * needs no fixing because the scheduler had not been called.
|
---|
[feb5915] | 669 | */
|
---|
[a7961271] | 670 | rdpr %otherwin, %l0
|
---|
| 671 | brnz %l0, 0f
|
---|
| 672 | nop
|
---|
[feb5915] | 673 |
|
---|
| 674 | /*
|
---|
[a7961271] | 675 | * OTHERWIN == 0
|
---|
[feb5915] | 676 | */
|
---|
| 677 |
|
---|
| 678 | /*
|
---|
[a7961271] | 679 | * If TSTATE.CWP + 1 == CWP, then we still do not have to fix CWP.
|
---|
[feb5915] | 680 | */
|
---|
[a7961271] | 681 | and %g1, TSTATE_CWP_MASK, %l0
|
---|
| 682 | inc %l0
|
---|
[84060e2] | 683 | and %l0, NWINDOWS - 1, %l0 ! %l0 mod NWINDOWS
|
---|
[a7961271] | 684 | rdpr %cwp, %l1
|
---|
| 685 | cmp %l0, %l1
|
---|
[577b531] | 686 | bz %xcc, 0f ! CWP is ok
|
---|
[a7961271] | 687 | nop
|
---|
| 688 |
|
---|
[feb5915] | 689 | /*
|
---|
[a7961271] | 690 | * Fix CWP.
|
---|
[cfa70add] | 691 | * In order to recapitulate, the input registers in the current
|
---|
| 692 | * window are the output registers of the window to which we want
|
---|
| 693 | * to restore. Because the fill trap fills only input and local
|
---|
[0fa6044] | 694 | * registers of a window, we need to preserve those output
|
---|
| 695 | * registers manually.
|
---|
[feb5915] | 696 | */
|
---|
[ee454eb] | 697 | mov %sp, %g2
|
---|
[d70ebffe] | 698 | stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
|
---|
| 699 | stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
|
---|
| 700 | stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
|
---|
| 701 | stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
|
---|
| 702 | stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
|
---|
| 703 | stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
|
---|
| 704 | stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
|
---|
| 705 | stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
|
---|
[a7961271] | 706 | wrpr %l0, 0, %cwp
|
---|
[ee454eb] | 707 | mov %g2, %sp
|
---|
[d70ebffe] | 708 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
|
---|
| 709 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
|
---|
| 710 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
|
---|
| 711 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
|
---|
| 712 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
|
---|
| 713 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
|
---|
| 714 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
|
---|
| 715 | ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
|
---|
[0fa6044] | 716 |
|
---|
[feb5915] | 717 | /*
|
---|
[a7961271] | 718 | * OTHERWIN != 0 or fall-through from the OTHERWIN == 0 case.
|
---|
[7bb6b06] | 719 | * The CWP has already been restored to the value it had after the SAVE
|
---|
[ee454eb] | 720 | * at the beginning of this function.
|
---|
| 721 | */
|
---|
| 722 | 0:
|
---|
[9314ee1] | 723 | .if NOT(\is_syscall)
|
---|
[ee454eb] | 724 | rdpr %tstate, %g1
|
---|
| 725 | andcc %g1, TSTATE_PRIV_BIT, %g0 ! if we are not returning to userspace...,
|
---|
[577b531] | 726 | bnz %xcc, 1f ! ...skip restoring userspace windows
|
---|
[ee454eb] | 727 | nop
|
---|
[9314ee1] | 728 | .endif
|
---|
[beb3926a] | 729 |
|
---|
| 730 | /*
|
---|
| 731 | * Spills and fills will be processed by the {spill,fill}_1_normal
|
---|
| 732 | * handlers.
|
---|
| 733 | */
|
---|
| 734 | wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
|
---|
[ed166f7] | 735 |
|
---|
| 736 | /*
|
---|
| 737 | * Set primary context according to secondary context.
|
---|
| 738 | */
|
---|
| 739 | wr %g0, ASI_DMMU, %asi
|
---|
| 740 | ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
|
---|
| 741 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
|
---|
[fd85ae5] | 742 | rd %pc, %g1
|
---|
| 743 | flush %g1
|
---|
[a35b458] | 744 |
|
---|
[ee454eb] | 745 | rdpr %cwp, %g1
|
---|
| 746 | rdpr %otherwin, %g2
|
---|
| 747 |
|
---|
| 748 | /*
|
---|
| 749 | * Skip all OTHERWIN windows and descend to the first window
|
---|
| 750 | * in the userspace window buffer.
|
---|
| 751 | */
|
---|
| 752 | sub %g1, %g2, %g3
|
---|
| 753 | dec %g3
|
---|
[84060e2] | 754 | and %g3, NWINDOWS - 1, %g3
|
---|
[ee454eb] | 755 | wrpr %g3, 0, %cwp
|
---|
| 756 |
|
---|
| 757 | /*
|
---|
| 758 | * CWP is now in the window last saved in the userspace window buffer.
|
---|
| 759 | * Fill all windows stored in the buffer.
|
---|
[feb5915] | 760 | */
|
---|
[ee454eb] | 761 | clr %g4
|
---|
[d364e94] | 762 | 0: andcc %g7, UWB_ALIGNMENT - 1, %g0 ! alignment check
|
---|
[577b531] | 763 | bz %xcc, 0f ! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill
|
---|
[ee454eb] | 764 | nop
|
---|
| 765 |
|
---|
| 766 | add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7
|
---|
| 767 | ldx [%g7 + L0_OFFSET], %l0
|
---|
| 768 | ldx [%g7 + L1_OFFSET], %l1
|
---|
| 769 | ldx [%g7 + L2_OFFSET], %l2
|
---|
| 770 | ldx [%g7 + L3_OFFSET], %l3
|
---|
| 771 | ldx [%g7 + L4_OFFSET], %l4
|
---|
| 772 | ldx [%g7 + L5_OFFSET], %l5
|
---|
| 773 | ldx [%g7 + L6_OFFSET], %l6
|
---|
| 774 | ldx [%g7 + L7_OFFSET], %l7
|
---|
| 775 | ldx [%g7 + I0_OFFSET], %i0
|
---|
| 776 | ldx [%g7 + I1_OFFSET], %i1
|
---|
| 777 | ldx [%g7 + I2_OFFSET], %i2
|
---|
| 778 | ldx [%g7 + I3_OFFSET], %i3
|
---|
| 779 | ldx [%g7 + I4_OFFSET], %i4
|
---|
| 780 | ldx [%g7 + I5_OFFSET], %i5
|
---|
| 781 | ldx [%g7 + I6_OFFSET], %i6
|
---|
| 782 | ldx [%g7 + I7_OFFSET], %i7
|
---|
| 783 |
|
---|
| 784 | dec %g3
|
---|
[84060e2] | 785 | and %g3, NWINDOWS - 1, %g3
|
---|
[ee454eb] | 786 | wrpr %g3, 0, %cwp ! switch to the preceeding window
|
---|
| 787 |
|
---|
[5646813] | 788 | ba %xcc, 0b
|
---|
[ee454eb] | 789 | inc %g4
|
---|
| 790 |
|
---|
[a7961271] | 791 | 0:
|
---|
[ee454eb] | 792 | /*
|
---|
| 793 | * Switch back to the proper current window and adjust
|
---|
| 794 | * OTHERWIN, CANRESTORE, CANSAVE and CLEANWIN.
|
---|
| 795 | */
|
---|
| 796 | wrpr %g1, 0, %cwp
|
---|
| 797 | add %g4, %g2, %g2
|
---|
[84060e2] | 798 | cmp %g2, NWINDOWS - 2
|
---|
[577b531] | 799 | bg %xcc, 2f ! fix the CANRESTORE=NWINDOWS-1 anomaly
|
---|
[84060e2] | 800 | mov NWINDOWS - 2, %g1 ! use dealy slot for both cases
|
---|
[ee454eb] | 801 | sub %g1, %g2, %g1
|
---|
[a35b458] | 802 |
|
---|
[ee454eb] | 803 | wrpr %g0, 0, %otherwin
|
---|
[84060e2] | 804 | wrpr %g1, 0, %cansave ! NWINDOWS - 2 - CANRESTORE
|
---|
[ee454eb] | 805 | wrpr %g2, 0, %canrestore ! OTHERWIN + windows in the buffer
|
---|
| 806 | wrpr %g2, 0, %cleanwin ! avoid information leak
|
---|
[a7961271] | 807 |
|
---|
[beb3926a] | 808 | 1:
|
---|
| 809 | restore
|
---|
[9314ee1] | 810 |
|
---|
| 811 | .if \is_syscall
|
---|
| 812 | done
|
---|
| 813 | .else
|
---|
[beb3926a] | 814 | retry
|
---|
[9314ee1] | 815 | .endif
|
---|
[beb3926a] | 816 |
|
---|
[ee454eb] | 817 | /*
|
---|
[beb3926a] | 818 | * We got here in order to avoid inconsistency of the window state registers.
|
---|
| 819 | * If the:
|
---|
| 820 | *
|
---|
[aef669b] | 821 | * save %g6, -ISTATE_SIZE, %sp
|
---|
[beb3926a] | 822 | *
|
---|
| 823 | * instruction trapped and spilled a register window into the userspace
|
---|
[84060e2] | 824 | * window buffer, we have just restored NWINDOWS - 1 register windows.
|
---|
[beb3926a] | 825 | * However, CANRESTORE can be only NWINDOW - 2 at most.
|
---|
| 826 | *
|
---|
[84060e2] | 827 | * The solution is to manually switch to (CWP - 1) mod NWINDOWS
|
---|
[beb3926a] | 828 | * and set the window state registers so that:
|
---|
| 829 | *
|
---|
[84060e2] | 830 | * CANRESTORE = NWINDOWS - 2
|
---|
| 831 | * CLEANWIN = NWINDOWS - 2
|
---|
[beb3926a] | 832 | * CANSAVE = 0
|
---|
| 833 | * OTHERWIN = 0
|
---|
| 834 | *
|
---|
[ab1ae2d9] | 835 | * The RESTORE instruction is therfore to be skipped.
|
---|
[ee454eb] | 836 | */
|
---|
[beb3926a] | 837 | 2:
|
---|
| 838 | wrpr %g0, 0, %otherwin
|
---|
| 839 | wrpr %g0, 0, %cansave
|
---|
| 840 | wrpr %g1, 0, %canrestore
|
---|
| 841 | wrpr %g1, 0, %cleanwin
|
---|
[ee454eb] | 842 |
|
---|
[beb3926a] | 843 | rdpr %cwp, %g1
|
---|
| 844 | dec %g1
|
---|
[84060e2] | 845 | and %g1, NWINDOWS - 1, %g1
|
---|
[beb3926a] | 846 | wrpr %g1, 0, %cwp ! CWP--
|
---|
[a35b458] | 847 |
|
---|
[9314ee1] | 848 | .if \is_syscall
|
---|
| 849 | done
|
---|
| 850 | .else
|
---|
[7614565] | 851 | retry
|
---|
[9314ee1] | 852 | .endif
|
---|
| 853 |
|
---|
| 854 | .endm
|
---|
| 855 |
|
---|
[a52e2f4] | 856 | SYMBOL(preemptible_handler)
|
---|
[9314ee1] | 857 | PREEMPTIBLE_HANDLER_TEMPLATE 0
|
---|
| 858 |
|
---|
[a52e2f4] | 859 | SYMBOL(trap_instruction_handler)
|
---|
[9314ee1] | 860 | PREEMPTIBLE_HANDLER_TEMPLATE 1
|
---|