[39494010] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Jakub Jermar
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[95c4776] | 3 | * Copyright (c) 2009 Pavel Rimsky
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[39494010] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[b6529ae] | 30 | /** @addtogroup sparc64interrupt
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[b45c443] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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[39494010] | 36 | #include <arch/interrupt.h>
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[f9a56c0] | 37 | #include <arch/trap/interrupt.h>
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[ec443d5] | 38 | #include <arch/trap/exception.h>
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[d70ebffe] | 39 | #include <arch/trap/mmu.h>
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[95c4776] | 40 | #include <arch/sparc64.h>
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[39494010] | 41 | #include <interrupt.h>
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[7dcf22a] | 42 | #include <ddi/irq.h>
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[83dab11] | 43 | #include <stdbool.h>
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[39494010] | 44 | #include <debug.h>
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[f9a56c0] | 45 | #include <arch/asm.h>
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[05882233] | 46 | #include <barrier.h>
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[ec443d5] | 47 | #include <arch/drivers/tick.h>
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[253f35a1] | 48 | #include <print.h>
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[00b38a3] | 49 | #include <arch.h>
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| 50 | #include <mm/tlb.h>
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| 51 | #include <config.h>
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[e3890b3f] | 52 | #include <synch/spinlock.h>
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[39494010] | 53 |
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[ec443d5] | 54 | void exc_arch_init(void)
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[39494010] | 55 | {
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[ec443d5] | 56 | exc_register(TT_INSTRUCTION_ACCESS_EXCEPTION,
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| 57 | "instruction_access_exception", false,
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| 58 | instruction_access_exception);
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| 59 | exc_register(TT_INSTRUCTION_ACCESS_ERROR,
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| 60 | "instruction_access_error", false,
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| 61 | instruction_access_error);
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[cade9c1] | 62 |
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| 63 | #ifdef SUN4V
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| 64 | exc_register(TT_IAE_UNAUTH_ACCESS,
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| 65 | "iae_unauth_access", false,
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| 66 | instruction_access_exception);
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| 67 | exc_register(TT_IAE_NFO_PAGE,
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| 68 | "iae_nfo_page", false,
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| 69 | instruction_access_exception);
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| 70 | #endif
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| 71 |
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[ec443d5] | 72 | exc_register(TT_ILLEGAL_INSTRUCTION,
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| 73 | "illegal_instruction", false,
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| 74 | illegal_instruction);
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| 75 | exc_register(TT_PRIVILEGED_OPCODE,
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| 76 | "privileged_opcode", false,
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| 77 | privileged_opcode);
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| 78 | exc_register(TT_UNIMPLEMENTED_LDD,
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| 79 | "unimplemented_LDD", false,
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| 80 | unimplemented_LDD);
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| 81 | exc_register(TT_UNIMPLEMENTED_STD,
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| 82 | "unimplemented_STD", false,
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| 83 | unimplemented_STD);
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[cade9c1] | 84 |
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| 85 | #ifdef SUN4V
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| 86 | exc_register(TT_DAE_INVALID_ASI,
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| 87 | "dae_invalid_asi", false,
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| 88 | data_access_exception);
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| 89 | exc_register(TT_DAE_PRIVILEGE_VIOLATION,
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| 90 | "dae_privilege_violation", false,
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| 91 | data_access_exception);
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| 92 | exc_register(TT_DAE_NC_PAGE,
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| 93 | "dae_nc_page", false,
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| 94 | data_access_exception);
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| 95 | exc_register(TT_DAE_NC_PAGE,
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| 96 | "dae_nc_page", false,
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| 97 | data_access_exception);
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| 98 | exc_register(TT_DAE_NFO_PAGE,
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| 99 | "dae_nfo_page", false,
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| 100 | data_access_exception);
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| 101 | #endif
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| 102 |
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[ec443d5] | 103 | exc_register(TT_FP_DISABLED,
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| 104 | "fp_disabled", true,
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| 105 | fp_disabled);
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| 106 | exc_register(TT_FP_EXCEPTION_IEEE_754,
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| 107 | "fp_exception_ieee_754", false,
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| 108 | fp_exception_ieee_754);
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| 109 | exc_register(TT_FP_EXCEPTION_OTHER,
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| 110 | "fp_exception_other", false,
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| 111 | fp_exception_other);
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| 112 | exc_register(TT_TAG_OVERFLOW,
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| 113 | "tag_overflow", false,
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[1b20da0] | 114 | tag_overflow);
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[ec443d5] | 115 | exc_register(TT_DIVISION_BY_ZERO,
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| 116 | "division_by_zero", false,
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| 117 | division_by_zero);
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| 118 | exc_register(TT_DATA_ACCESS_EXCEPTION,
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| 119 | "data_access_exception", false,
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| 120 | data_access_exception);
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| 121 | exc_register(TT_DATA_ACCESS_ERROR,
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| 122 | "data_access_error", false,
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| 123 | data_access_error);
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| 124 | exc_register(TT_MEM_ADDRESS_NOT_ALIGNED,
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| 125 | "mem_address_not_aligned", false,
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| 126 | mem_address_not_aligned);
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| 127 | exc_register(TT_LDDF_MEM_ADDRESS_NOT_ALIGNED,
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| 128 | "LDDF_mem_address_not_aligned", false,
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| 129 | LDDF_mem_address_not_aligned);
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| 130 | exc_register(TT_STDF_MEM_ADDRESS_NOT_ALIGNED,
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| 131 | "STDF_mem_address_not_aligned", false,
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| 132 | STDF_mem_address_not_aligned);
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| 133 | exc_register(TT_PRIVILEGED_ACTION,
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| 134 | "privileged_action", false,
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| 135 | privileged_action);
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| 136 | exc_register(TT_LDQF_MEM_ADDRESS_NOT_ALIGNED,
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| 137 | "LDQF_mem_address_not_aligned", false,
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| 138 | LDQF_mem_address_not_aligned);
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| 139 | exc_register(TT_STQF_MEM_ADDRESS_NOT_ALIGNED,
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| 140 | "STQF_mem_address_not_aligned", false,
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| 141 | STQF_mem_address_not_aligned);
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| 142 |
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| 143 | exc_register(TT_INTERRUPT_LEVEL_14,
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| 144 | "interrupt_level_14", true,
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| 145 | tick_interrupt);
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| 146 |
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[1b20da0] | 147 | #ifdef SUN4U
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[ec443d5] | 148 | exc_register(TT_INTERRUPT_VECTOR_TRAP,
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| 149 | "interrupt_vector_trap", true,
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| 150 | interrupt);
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| 151 | #endif
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[d70ebffe] | 152 |
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| 153 | exc_register(TT_FAST_INSTRUCTION_ACCESS_MMU_MISS,
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| 154 | "fast_instruction_access_mmu_miss", true,
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| 155 | fast_instruction_access_mmu_miss);
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| 156 | exc_register(TT_FAST_DATA_ACCESS_MMU_MISS,
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| 157 | "fast_data_access_mmu_miss", true,
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| 158 | fast_data_access_mmu_miss);
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| 159 | exc_register(TT_FAST_DATA_ACCESS_PROTECTION,
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| 160 | "fast_data_access_protection", true,
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[1b20da0] | 161 | fast_data_access_protection);
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[cade9c1] | 162 |
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| 163 | #ifdef SUN4V
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| 164 | exc_register(TT_CPU_MONDO,
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| 165 | "cpu_mondo", true,
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| 166 | cpu_mondo);
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| 167 | #endif
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| 168 |
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[39494010] | 169 | }
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[b3b7e14a] | 170 |
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[3222efd] | 171 | /** @}
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[b45c443] | 172 | */
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