source: mainline/kernel/arch/sparc64/src/mm/tsb.c@ b60c582

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b60c582 was 965dc18, checked in by Jakub Jermar <jakub@…>, 17 years ago

Merge sparc branch to trunk.
  • Property mode set to 100644
File size: 5.0 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tsb.h>
36#include <arch/mm/tlb.h>
37#include <arch/mm/page.h>
38#include <arch/barrier.h>
39#include <mm/as.h>
40#include <arch/types.h>
41#include <macros.h>
42#include <debug.h>
43
44#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
45
46/** Invalidate portion of TSB.
47 *
48 * We assume that the address space is already locked. Note that respective
49 * portions of both TSBs are invalidated at a time.
50 *
51 * @param as Address space.
52 * @param page First page to invalidate in TSB.
53 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
54 * whole TSB.
55 */
56void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
57{
58 index_t i0, i;
59 count_t cnt;
60
61 ASSERT(as->arch.itsb && as->arch.dtsb);
62
63 i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
64 ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
65
66 if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
67 cnt = ITSB_ENTRY_COUNT;
68 else
69 cnt = pages * 2;
70
71 for (i = 0; i < cnt; i++) {
72 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
73 true;
74 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
75 true;
76 }
77}
78
79/** Copy software PTE to ITSB.
80 *
81 * @param t Software PTE.
82 * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
83 */
84void itsb_pte_copy(pte_t *t, index_t index)
85{
86 as_t *as;
87 tsb_entry_t *tsb;
88 index_t entry;
89
90 ASSERT(index <= 1);
91
92 as = t->as;
93 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
94 ASSERT(entry < ITSB_ENTRY_COUNT);
95 tsb = &as->arch.itsb[entry];
96
97 /*
98 * We use write barriers to make sure that the TSB load
99 * won't use inconsistent data or that the fault will
100 * be repeated.
101 */
102
103 tsb->tag.invalid = true; /* invalidate the entry
104 * (tag target has this
105 * set to 0) */
106
107 write_barrier();
108
109 tsb->tag.context = as->asid;
110 /* the shift is bigger than PAGE_WIDTH, do not bother with index */
111 tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
112 tsb->data.value = 0;
113 tsb->data.size = PAGESIZE_8K;
114 tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
115 tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */
116 tsb->data.p = t->k; /* p as privileged, k as kernel */
117 tsb->data.v = t->p; /* v as valid, p as present */
118
119 write_barrier();
120
121 tsb->tag.invalid = false; /* mark the entry as valid */
122}
123
124/** Copy software PTE to DTSB.
125 *
126 * @param t Software PTE.
127 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
128 * @param ro If true, the mapping is copied read-only.
129 */
130void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
131{
132 as_t *as;
133 tsb_entry_t *tsb;
134 index_t entry;
135
136 ASSERT(index <= 1);
137
138 as = t->as;
139 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
140 ASSERT(entry < DTSB_ENTRY_COUNT);
141 tsb = &as->arch.dtsb[entry];
142
143 /*
144 * We use write barriers to make sure that the TSB load
145 * won't use inconsistent data or that the fault will
146 * be repeated.
147 */
148
149 tsb->tag.invalid = true; /* invalidate the entry
150 * (tag target has this
151 * set to 0) */
152
153 write_barrier();
154
155 tsb->tag.context = as->asid;
156 /* the shift is bigger than PAGE_WIDTH, do not bother with index */
157 tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
158 tsb->data.value = 0;
159 tsb->data.size = PAGESIZE_8K;
160 tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
161 tsb->data.cp = t->c;
162#ifdef CONFIG_VIRT_IDX_DCACHE
163 tsb->data.cv = t->c;
164#endif /* CONFIG_VIRT_IDX_DCACHE */
165 tsb->data.p = t->k; /* p as privileged */
166 tsb->data.w = ro ? false : t->w;
167 tsb->data.v = t->p;
168
169 write_barrier();
170
171 tsb->tag.invalid = false; /* mark the entry as valid */
172}
173
174/** @}
175 */
176
Note: See TracBrowser for help on using the repository browser.