source: mainline/kernel/arch/sparc64/include/mm/tsb.h@ 57da95c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 57da95c was 57da95c, checked in by Jakub Jermar <jakub@…>, 19 years ago
  • Create a dedicated slab cache for as_t objects and switch from malloc/free to slab_alloc/slab_free for

them.

  • Slightly fix and improve both the kernel and userspace atomic_add() on sparc64.
  • More TSB work on the sparc64 front.
  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 * Copyright (C) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_sparc64_TSB_H_
36#define KERN_sparc64_TSB_H_
37
38#include <arch/mm/tte.h>
39#include <arch/mm/mmu.h>
40#include <arch/types.h>
41#include <typedefs.h>
42
43/*
44 * ITSB abd DTSB will claim 64K of memory, which
45 * is a nice number considered that it is one of
46 * the page sizes supported by hardware, which,
47 * again, is nice because TSBs need to be locked
48 * in TLBs - only one TLB entry will do.
49 */
50#define TSB_SIZE 2 /* when changing this, change as.c as well */
51#define ITSB_ENTRY_COUNT (512*(1<<TSB_SIZE))
52#define DTSB_ENTRY_COUNT (512*(1<<TSB_SIZE))
53
54struct tsb_entry {
55 tte_tag_t tag;
56 tte_data_t data;
57} __attribute__ ((packed));
58typedef struct tsb_entry tsb_entry_t;
59
60/** TSB Base register. */
61union tsb_base_reg {
62 uint64_t value;
63 struct {
64 uint64_t base : 51; /**< TSB base address, bits 63:13. */
65 unsigned split : 1; /**< Split vs. common TSB for 8K and 64K pages.
66 * HelenOS uses only 8K pages for user mappings,
67 * so we always set this to 0.
68 */
69 unsigned : 9;
70 unsigned size : 3; /**< TSB size. Number of entries is 512*2^size. */
71 } __attribute__ ((packed));
72};
73typedef union tsb_base_reg tsb_base_reg_t;
74
75/** Read ITSB Base register.
76 *
77 * @return Content of the ITSB Base register.
78 */
79static inline uint64_t itsb_base_read(void)
80{
81 return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
82}
83
84/** Read DTSB Base register.
85 *
86 * @return Content of the DTSB Base register.
87 */
88static inline uint64_t dtsb_base_read(void)
89{
90 return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
91}
92
93/** Write ITSB Base register.
94 *
95 * @param v New content of the ITSB Base register.
96 */
97static inline void itsb_base_write(uint64_t v)
98{
99 asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
100}
101
102/** Write DTSB Base register.
103 *
104 * @param v New content of the DTSB Base register.
105 */
106static inline void dtsb_base_write(uint64_t v)
107{
108 asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
109}
110
111extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages);
112
113#endif
114
115/** @}
116 */
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