source: mainline/kernel/arch/sparc64/include/barrier.h@ b006a2c8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b006a2c8 was b3e8c90, checked in by Jakub Jermar <jakub@…>, 19 years ago

sparc64 work.

  1. Formatting fixes.
  2. When writing to DMMU ASI's, simple membar() can be used in place of flush().
  3. Substantial changes in the way the TLB is taken over.
  4. Remove unneeded functions.

This is the first revision that also runs on a real world Ultra 5 with UltraSPARC IIi
processor.

Note that 3. needs further work as the current implementation depends on the fact
that the compiler will use registers for local variables in take_over_tlb_and_tt().
Rewrite of that function into assembly is to follow.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef __sparc64_BARRIER_H__
36#define __sparc64_BARRIER_H__
37
38/*
39 * TODO: Implement true SPARC V9 memory barriers for macros below.
40 */
41#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
42#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
43
44#define memory_barrier()
45#define read_barrier()
46#define write_barrier()
47
48/** Flush Instruction Memory instruction. */
49static inline void flush(void)
50{
51 /*
52 * The FLUSH instruction takes address parameter.
53 * As such, it may trap if the address is not found in DTLB.
54 * However, JPS1 implementations are free to ignore the trap.
55 */
56
57 __asm__ volatile ("flush %0\n" :: "r" (0x400000));
58}
59
60/** Memory Barrier instruction. */
61static inline void membar(void)
62{
63 __asm__ volatile ("membar #Sync\n");
64}
65
66#endif
67
68/** @}
69 */
Note: See TracBrowser for help on using the repository browser.