source: mainline/kernel/arch/ppc32/src/mm/tlb.c@ 55896b6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 55896b6 was 655f70b, checked in by Martin Decky <martin@…>, 14 years ago

ppc32: reimplement tlb_invalidate_all, this finally allows a real-world PowerPC G4 machine to operate correctly
(the original inline assembly with the .rept directive did not inline correctly and it wiped out the first TLB entry 64 times instead of wiping all 64 entries)

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <interrupt.h>
37#include <typedefs.h>
38
39void tlb_refill(unsigned int n, istate_t *istate)
40{
41 uint32_t tlbmiss;
42 ptehi_t ptehi;
43 ptelo_t ptelo;
44
45 asm volatile (
46 "mfspr %[tlbmiss], 980\n"
47 "mfspr %[ptehi], 981\n"
48 "mfspr %[ptelo], 982\n"
49 : [tlbmiss] "=r" (tlbmiss),
50 [ptehi] "=r" (ptehi),
51 [ptelo] "=r" (ptelo)
52 );
53
54 uint32_t badvaddr = tlbmiss & 0xfffffffc;
55 uint32_t physmem = physmem_top();
56
57 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
58 return; // FIXME
59
60 ptelo.rpn = KA2PA(badvaddr) >> 12;
61 ptelo.wimg = 0;
62 ptelo.pp = 2; // FIXME
63
64 uint32_t index = 0;
65 asm volatile (
66 "mtspr 981, %[ptehi]\n"
67 "mtspr 982, %[ptelo]\n"
68 "tlbld %[index]\n"
69 "tlbli %[index]\n"
70 : [index] "=r" (index)
71 : [ptehi] "r" (ptehi),
72 [ptelo] "r" (ptelo)
73 );
74}
75
76void tlb_arch_init(void)
77{
78 tlb_invalidate_all();
79}
80
81void tlb_invalidate_all(void)
82{
83 asm volatile (
84 "sync\n"
85 );
86
87 for (unsigned int i = 0; i < 0x00040000; i += 0x00001000) {
88 asm volatile (
89 "tlbie %[i]\n"
90 :: [i] "r" (i)
91 );
92 }
93
94 asm volatile (
95 "eieio\n"
96 "tlbsync\n"
97 "sync\n"
98 );
99}
100
101void tlb_invalidate_asid(asid_t asid)
102{
103 tlb_invalidate_all();
104}
105
106void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
107{
108 tlb_invalidate_all();
109}
110
111#define PRINT_BAT(name, ureg, lreg) \
112 asm volatile ( \
113 "mfspr %[upper], " #ureg "\n" \
114 "mfspr %[lower], " #lreg "\n" \
115 : [upper] "=r" (upper), \
116 [lower] "=r" (lower) \
117 ); \
118 \
119 mask = (upper & 0x1ffc) >> 2; \
120 if (upper & 3) { \
121 uint32_t tmp = mask; \
122 length = 128; \
123 \
124 while (tmp) { \
125 if ((tmp & 1) == 0) { \
126 printf("ibat[0]: error in mask\n"); \
127 break; \
128 } \
129 length <<= 1; \
130 tmp >>= 1; \
131 } \
132 } else \
133 length = 0; \
134 \
135 printf(name ": page=%#0" PRIx32 " frame=%#0" PRIx32 \
136 " length=%#0" PRIx32 " KB (mask=%#0" PRIx32 ")%s%s\n", \
137 upper & UINT32_C(0xffff0000), lower & UINT32_C(0xffff0000), \
138 length, mask, \
139 ((upper >> 1) & 1) ? " supervisor" : "", \
140 (upper & 1) ? " user" : "");
141
142void tlb_print(void)
143{
144 uint32_t sr;
145
146 for (sr = 0; sr < 16; sr++) {
147 uint32_t vsid = sr_get(sr << 28);
148
149 printf("sr[%02" PRIu32 "]: vsid=%#0" PRIx32 " (asid=%" PRIu32 ")"
150 "%s%s\n", sr, vsid & UINT32_C(0x00ffffff),
151 (vsid & UINT32_C(0x00ffffff)) >> 4,
152 ((vsid >> 30) & 1) ? " supervisor" : "",
153 ((vsid >> 29) & 1) ? " user" : "");
154 }
155
156 uint32_t upper;
157 uint32_t lower;
158 uint32_t mask;
159 uint32_t length;
160
161 PRINT_BAT("ibat[0]", 528, 529);
162 PRINT_BAT("ibat[1]", 530, 531);
163 PRINT_BAT("ibat[2]", 532, 533);
164 PRINT_BAT("ibat[3]", 534, 535);
165
166 PRINT_BAT("dbat[0]", 536, 537);
167 PRINT_BAT("dbat[1]", 538, 539);
168 PRINT_BAT("dbat[2]", 540, 541);
169 PRINT_BAT("dbat[3]", 542, 543);
170}
171
172/** @}
173 */
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