source: mainline/kernel/arch/ppc32/src/exception.S@ a35b458

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a35b458 was a35b458, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 8 years ago

style: Remove trailing whitespace on _all_ lines, including empty ones, for particular file types.

Command used: tools/srepl '\s\+$' '' -- *.c *.h *.py *.sh *.s *.S *.ag

Currently, whitespace on empty lines is very inconsistent.
There are two basic choices: Either remove the whitespace, or keep empty lines
indented to the level of surrounding code. The former is AFAICT more common,
and also much easier to do automatically.

Alternatively, we could write script for automatic indentation, and use that
instead. However, if such a script exists, it's possible to use the indented
style locally, by having the editor apply relevant conversions on load/save,
without affecting remote repository. IMO, it makes more sense to adopt
the simpler rule.

  • Property mode set to 100644
File size: 5.6 KB
RevLine 
[edc89bd0]1#
[df4ed85]2# Copyright (c) 2006 Martin Decky
[edc89bd0]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[b66cc97]29#include <abi/asmtool.h>
[edc89bd0]30#include <arch/asm/regname.h>
[c0699467]31#include <arch/msr.h>
[91d5ad6]32#include <arch/mm/page.h>
[beb16cfa]33#include <arch/istate_struct.h>
34#include <arch/stack.h>
[0871296]35#include <align.h>
[edc89bd0]36
37.section K_UNMAPPED_TEXT_START, "ax"
38
[613bc54]39.macro CONTEXT_STORE
[a35b458]40
[ffe276f]41 # save r12 in SPRG1, backup CR in r12
[e34a141]42 # save SP in SPRG2
[a35b458]43
[e34a141]44 mtsprg1 r12
[762a824]45 mfcr r12
[e34a141]46 mtsprg2 sp
[a35b458]47
[0871296]48 # check whether the previous mode was user or kernel
[a35b458]49
[0871296]50 mfsrr1 sp # use sp as a temporary register to hold SRR1
[1b20da0]51 andi. sp, sp, MSR_PR
[762a824]52 bne 1f
[0871296]53 # previous mode was kernel
[a35b458]54
[0871296]55 mfsprg2 sp
56 subis sp, sp, 0x8000
[762a824]57 b 2f
[a35b458]58
[762a824]59 1:
[0871296]60 # previous mode was user
[a35b458]61
[0871296]62 mfsprg0 sp
[762a824]63 2:
[a35b458]64
[beb16cfa]65 subi sp, sp, ALIGN_UP(ISTATE_SIZE, STACK_ALIGNMENT)
66 stw r0, ISTATE_OFFSET_R0(sp)
67 stw r2, ISTATE_OFFSET_R2(sp)
68 stw r3, ISTATE_OFFSET_R3(sp)
69 stw r4, ISTATE_OFFSET_R4(sp)
70 stw r5, ISTATE_OFFSET_R5(sp)
71 stw r6, ISTATE_OFFSET_R6(sp)
72 stw r7, ISTATE_OFFSET_R7(sp)
73 stw r8, ISTATE_OFFSET_R8(sp)
74 stw r9, ISTATE_OFFSET_R9(sp)
75 stw r10, ISTATE_OFFSET_R10(sp)
76 stw r11, ISTATE_OFFSET_R11(sp)
77 stw r13, ISTATE_OFFSET_R13(sp)
78 stw r14, ISTATE_OFFSET_R14(sp)
79 stw r15, ISTATE_OFFSET_R15(sp)
80 stw r16, ISTATE_OFFSET_R16(sp)
81 stw r17, ISTATE_OFFSET_R17(sp)
82 stw r18, ISTATE_OFFSET_R18(sp)
83 stw r19, ISTATE_OFFSET_R19(sp)
84 stw r20, ISTATE_OFFSET_R20(sp)
85 stw r21, ISTATE_OFFSET_R21(sp)
86 stw r22, ISTATE_OFFSET_R22(sp)
87 stw r23, ISTATE_OFFSET_R23(sp)
88 stw r24, ISTATE_OFFSET_R24(sp)
89 stw r25, ISTATE_OFFSET_R25(sp)
90 stw r26, ISTATE_OFFSET_R26(sp)
91 stw r27, ISTATE_OFFSET_R27(sp)
92 stw r28, ISTATE_OFFSET_R28(sp)
93 stw r29, ISTATE_OFFSET_R29(sp)
94 stw r30, ISTATE_OFFSET_R30(sp)
95 stw r31, ISTATE_OFFSET_R31(sp)
[a35b458]96
[beb16cfa]97 stw r12, ISTATE_OFFSET_CR(sp)
[a35b458]98
[e34a141]99 mfsrr0 r12
[beb16cfa]100 stw r12, ISTATE_OFFSET_PC(sp)
[a35b458]101
[e34a141]102 mfsrr1 r12
[beb16cfa]103 stw r12, ISTATE_OFFSET_SRR1(sp)
[a35b458]104
[e34a141]105 mflr r12
[beb16cfa]106 stw r12, ISTATE_OFFSET_LR(sp)
[a35b458]107
[e34a141]108 mfctr r12
[beb16cfa]109 stw r12, ISTATE_OFFSET_CTR(sp)
[a35b458]110
[e34a141]111 mfxer r12
[beb16cfa]112 stw r12, ISTATE_OFFSET_XER(sp)
[a35b458]113
[826c203]114 mfdar r12
[beb16cfa]115 stw r12, ISTATE_OFFSET_DAR(sp)
[a35b458]116
[826c203]117 mfsprg1 r12
[beb16cfa]118 stw r12, ISTATE_OFFSET_R12(sp)
[a35b458]119
[826c203]120 mfsprg2 r12
[beb16cfa]121 stw r12, ISTATE_OFFSET_SP(sp)
[3ab2d1e]122
123 li r12, 0
[beb16cfa]124 stw r12, ISTATE_OFFSET_LR_FRAME(sp)
125 stw r12, ISTATE_OFFSET_SP_FRAME(sp)
[613bc54]126.endm
127
128.org 0x100
[b66cc97]129SYMBOL(exc_system_reset)
[c782434]130 CONTEXT_STORE
[a35b458]131
[c782434]132 li r3, 0
133 b jump_to_kernel
[613bc54]134
135.org 0x200
[b66cc97]136SYMBOL(exc_machine_check)
[c782434]137 CONTEXT_STORE
[a35b458]138
[c782434]139 li r3, 1
140 b jump_to_kernel
[613bc54]141
142.org 0x300
[b66cc97]143SYMBOL(exc_data_storage)
[613bc54]144 CONTEXT_STORE
[a35b458]145
[6c3106f]146 li r3, 2
147 b jump_to_kernel
[613bc54]148
149.org 0x400
[b66cc97]150SYMBOL(exc_instruction_storage)
[762a824]151 CONTEXT_STORE
[a35b458]152
[6c3106f]153 li r3, 3
154 b jump_to_kernel
[613bc54]155
156.org 0x500
[b66cc97]157SYMBOL(exc_external)
[982f0fe]158 CONTEXT_STORE
[a35b458]159
[c782434]160 li r3, 4
[982f0fe]161 b jump_to_kernel
[613bc54]162
163.org 0x600
[b66cc97]164SYMBOL(exc_alignment)
[c782434]165 CONTEXT_STORE
[a35b458]166
[c782434]167 li r3, 5
168 b jump_to_kernel
[613bc54]169
170.org 0x700
[b66cc97]171SYMBOL(exc_program)
[c782434]172 CONTEXT_STORE
[a35b458]173
[c782434]174 li r3, 6
175 b jump_to_kernel
[613bc54]176
177.org 0x800
[b66cc97]178SYMBOL(exc_fp_unavailable)
[c782434]179 CONTEXT_STORE
[a35b458]180
[c782434]181 li r3, 7
182 b jump_to_kernel
[613bc54]183
184.org 0x900
[b66cc97]185SYMBOL(exc_decrementer)
[a33c990]186 CONTEXT_STORE
[a35b458]187
[c782434]188 li r3, 8
[e34a141]189 b jump_to_kernel
[edc89bd0]190
191.org 0xa00
[b66cc97]192SYMBOL(exc_reserved0)
[c782434]193 CONTEXT_STORE
[a35b458]194
[c782434]195 li r3, 9
196 b jump_to_kernel
[edc89bd0]197
198.org 0xb00
[b66cc97]199SYMBOL(exc_reserved1)
[c782434]200 CONTEXT_STORE
[a35b458]201
[c782434]202 li r3, 10
203 b jump_to_kernel
[edc89bd0]204
205.org 0xc00
[b66cc97]206SYMBOL(exc_syscall)
[0867321]207 CONTEXT_STORE
[a35b458]208
[e34a141]209 b jump_to_kernel_syscall
[edc89bd0]210
211.org 0xd00
[b66cc97]212SYMBOL(exc_trace)
[c782434]213 CONTEXT_STORE
[a35b458]214
[c782434]215 li r3, 12
216 b jump_to_kernel
[898d9f8]217
[0867321]218.org 0x1000
[b66cc97]219SYMBOL(exc_itlb_miss)
[0867321]220 CONTEXT_STORE
[a35b458]221
[6c3106f]222 li r3, 13
223 b jump_to_kernel
[0867321]224
225.org 0x1100
[b66cc97]226SYMBOL(exc_dtlb_miss_load)
[0867321]227 CONTEXT_STORE
[a35b458]228
[6c3106f]229 li r3, 14
230 b jump_to_kernel
[0867321]231
232.org 0x1200
[b66cc97]233SYMBOL(exc_dtlb_miss_store)
[0867321]234 CONTEXT_STORE
[a35b458]235
[6c3106f]236 li r3, 15
[826c203]237 b jump_to_kernel
238
[6c3106f]239.org 0x4000
[898d9f8]240jump_to_kernel:
[3fde837]241 mfsrr1 r5
242 andi. r5, r5, MSR_PR
243 bne 1f
244 # Previous mode was kernel.
245 # We can construct a proper frame linkage.
[a35b458]246
[3fde837]247 mfsrr0 r12
248 stw r12, ISTATE_OFFSET_LR_FRAME(sp)
249 mfsprg2 r12
250 stw r12, ISTATE_OFFSET_SP_FRAME(sp)
251 1:
252
[898d9f8]253 lis r12, iret@ha
254 addi r12, r12, iret@l
255 mtlr r12
[3fde837]256
[fbb8b2b]257 lis r12, exc_dispatch@ha
258 addi r12, r12, exc_dispatch@l
259 mtsrr0 r12
[0871296]260
[898d9f8]261 mfmsr r12
[3fde837]262 mfsrr1 r5
263 andi. r5, r5, MSR_FP
[df7f5cea]264 or r12, r12, r5 # Propagate MSR_FP from SRR1 to MSR
[3fde837]265 ori r12, r12, (MSR_IR | MSR_DR)
[898d9f8]266 mtsrr1 r12
[a35b458]267
[898d9f8]268 addis sp, sp, 0x8000
269 mr r4, sp
[a35b458]270
[898d9f8]271 rfi
272
273jump_to_kernel_syscall:
274 lis r12, syscall_handler@ha
275 addi r12, r12, syscall_handler@l
276 mtsrr0 r12
[a35b458]277
[898d9f8]278 lis r12, iret_syscall@ha
279 addi r12, r12, iret_syscall@l
280 mtlr r12
[df7f5cea]281
282 mfsrr1 r0
283 andi. r0, r0, MSR_FP
[898d9f8]284 mfmsr r12
[df7f5cea]285 or r12, r12, r0 # Propagate MSR_FP from SRR1 to MSR
[8c7d5ad]286 ori r12, r12, (MSR_IR | MSR_DR | MSR_EE)
[898d9f8]287 mtsrr1 r12
[a35b458]288
[898d9f8]289 addis sp, sp, 0x8000
290 rfi
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