source: mainline/kernel/arch/ppc32/src/asm.S@ 1b20da0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 1b20da0 was b66cc97, checked in by Jakub Jermar <jakub@…>, 9 years ago

ppc32: use asmtool.h macros for defining symbols
  • Property mode set to 100644
File size: 5.6 KB
RevLine 
[eedf4c5]1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[efa9b73]28
[b66cc97]29#include <abi/asmtool.h>
[37c8975]30#include <arch/asm/regname.h>
[c0699467]31#include <arch/msr.h>
[beb16cfa]32#include <arch/istate_struct.h>
[10caad0]33
[efa9b73]34.text
35
[b66cc97]36FUNCTION_BEGIN(userspace_asm)
[eedf4c5]37 /*
38 * r3 = uspace_uarg
39 * r4 = stack
40 * r5 = entry
41 */
[762a824]42
[eedf4c5]43 /* Disable interrupts */
[ffe276f]44
[e692a27]45 mfmsr r31
46 rlwinm r31, r31, 0, 17, 15
47 mtmsr r31
[5a42886]48 isync
[e692a27]49
[eedf4c5]50 /* Set entry point */
[e692a27]51
52 mtsrr0 r5
53
[52c0b8c]54 /* Set privileged state, enable interrupts */
[e692a27]55
[ffe276f]56 ori r31, r31, MSR_PR
57 ori r31, r31, MSR_EE
[e692a27]58 mtsrr1 r31
59
[eedf4c5]60 /* Set stack */
[e692a27]61
62 mr sp, r4
[ffe276f]63
[eedf4c5]64 /* %r6 is defined to hold pcb_ptr - set it to 0 */
[ffe276f]65
[c1b455e]66 xor r6, r6, r6
[e692a27]67
[eedf4c5]68 /* Jump to userspace */
[e692a27]69
70 rfi
[b66cc97]71FUNCTION_END(userspace_asm)
[e692a27]72
[b66cc97]73SYMBOL(iret)
[eedf4c5]74 /* Disable interrupts */
[e34a141]75
76 mfmsr r31
77 rlwinm r31, r31, 0, 17, 15
78 mtmsr r31
[5a42886]79 isync
[e34a141]80
[beb16cfa]81 lwz r0, ISTATE_OFFSET_R0(sp)
82 lwz r2, ISTATE_OFFSET_R2(sp)
83 lwz r3, ISTATE_OFFSET_R3(sp)
84 lwz r4, ISTATE_OFFSET_R4(sp)
85 lwz r5, ISTATE_OFFSET_R5(sp)
86 lwz r6, ISTATE_OFFSET_R6(sp)
87 lwz r7, ISTATE_OFFSET_R7(sp)
88 lwz r8, ISTATE_OFFSET_R8(sp)
89 lwz r9, ISTATE_OFFSET_R9(sp)
90 lwz r10, ISTATE_OFFSET_R10(sp)
91 lwz r11, ISTATE_OFFSET_R11(sp)
92 lwz r13, ISTATE_OFFSET_R13(sp)
93 lwz r14, ISTATE_OFFSET_R14(sp)
94 lwz r15, ISTATE_OFFSET_R15(sp)
95 lwz r16, ISTATE_OFFSET_R16(sp)
96 lwz r17, ISTATE_OFFSET_R17(sp)
97 lwz r18, ISTATE_OFFSET_R18(sp)
98 lwz r19, ISTATE_OFFSET_R19(sp)
99 lwz r20, ISTATE_OFFSET_R20(sp)
100 lwz r21, ISTATE_OFFSET_R21(sp)
101 lwz r22, ISTATE_OFFSET_R22(sp)
102 lwz r23, ISTATE_OFFSET_R23(sp)
103 lwz r24, ISTATE_OFFSET_R24(sp)
104 lwz r25, ISTATE_OFFSET_R25(sp)
105 lwz r26, ISTATE_OFFSET_R26(sp)
106 lwz r27, ISTATE_OFFSET_R27(sp)
107 lwz r28, ISTATE_OFFSET_R28(sp)
108 lwz r29, ISTATE_OFFSET_R29(sp)
109 lwz r30, ISTATE_OFFSET_R30(sp)
110 lwz r31, ISTATE_OFFSET_R31(sp)
111
112 lwz r12, ISTATE_OFFSET_CR(sp)
[e34a141]113 mtcr r12
[762a824]114
[beb16cfa]115 lwz r12, ISTATE_OFFSET_PC(sp)
[e34a141]116 mtsrr0 r12
[762a824]117
[beb16cfa]118 lwz r12, ISTATE_OFFSET_SRR1(sp)
[e34a141]119 mtsrr1 r12
[762a824]120
[beb16cfa]121 lwz r12, ISTATE_OFFSET_LR(sp)
[e34a141]122 mtlr r12
[762a824]123
[beb16cfa]124 lwz r12, ISTATE_OFFSET_CTR(sp)
[762a824]125 mtctr r12
126
[beb16cfa]127 lwz r12, ISTATE_OFFSET_XER(sp)
[762a824]128 mtxer r12
[e34a141]129
[beb16cfa]130 lwz r12, ISTATE_OFFSET_R12(sp)
131 lwz sp, ISTATE_OFFSET_SP(sp)
[e34a141]132
133 rfi
[762a824]134
[b66cc97]135SYMBOL(iret_syscall)
[eedf4c5]136 /* Disable interrupts */
[e34a141]137
138 mfmsr r31
139 rlwinm r31, r31, 0, 17, 15
140 mtmsr r31
[5a42886]141 isync
[e34a141]142
[beb16cfa]143 lwz r0, ISTATE_OFFSET_R0(sp)
144 lwz r2, ISTATE_OFFSET_R2(sp)
145 lwz r4, ISTATE_OFFSET_R4(sp)
146 lwz r5, ISTATE_OFFSET_R5(sp)
147 lwz r6, ISTATE_OFFSET_R6(sp)
148 lwz r7, ISTATE_OFFSET_R7(sp)
149 lwz r8, ISTATE_OFFSET_R8(sp)
150 lwz r9, ISTATE_OFFSET_R9(sp)
151 lwz r10, ISTATE_OFFSET_R10(sp)
152 lwz r11, ISTATE_OFFSET_R11(sp)
153 lwz r13, ISTATE_OFFSET_R13(sp)
154 lwz r14, ISTATE_OFFSET_R14(sp)
155 lwz r15, ISTATE_OFFSET_R15(sp)
156 lwz r16, ISTATE_OFFSET_R16(sp)
157 lwz r17, ISTATE_OFFSET_R17(sp)
158 lwz r18, ISTATE_OFFSET_R18(sp)
159 lwz r19, ISTATE_OFFSET_R19(sp)
160 lwz r20, ISTATE_OFFSET_R20(sp)
161 lwz r21, ISTATE_OFFSET_R21(sp)
162 lwz r22, ISTATE_OFFSET_R22(sp)
163 lwz r23, ISTATE_OFFSET_R23(sp)
164 lwz r24, ISTATE_OFFSET_R24(sp)
165 lwz r25, ISTATE_OFFSET_R25(sp)
166 lwz r26, ISTATE_OFFSET_R26(sp)
167 lwz r27, ISTATE_OFFSET_R27(sp)
168 lwz r28, ISTATE_OFFSET_R28(sp)
169 lwz r29, ISTATE_OFFSET_R29(sp)
170 lwz r30, ISTATE_OFFSET_R30(sp)
171 lwz r31, ISTATE_OFFSET_R31(sp)
172
173 lwz r12, ISTATE_OFFSET_CR(sp)
[e34a141]174 mtcr r12
175
[beb16cfa]176 lwz r12, ISTATE_OFFSET_PC(sp)
[e34a141]177 mtsrr0 r12
178
[beb16cfa]179 lwz r12, ISTATE_OFFSET_SRR1(sp)
[e34a141]180 mtsrr1 r12
181
[beb16cfa]182 lwz r12, ISTATE_OFFSET_LR(sp)
[e34a141]183 mtlr r12
184
[beb16cfa]185 lwz r12, ISTATE_OFFSET_CTR(sp)
[e34a141]186 mtctr r12
187
[beb16cfa]188 lwz r12, ISTATE_OFFSET_XER(sp)
[e34a141]189 mtxer r12
190
[beb16cfa]191 lwz r12, ISTATE_OFFSET_R12(sp)
192 lwz sp, ISTATE_OFFSET_SP(sp)
[ffe276f]193
[91d5ad6]194 rfi
[b60c582]195
[b66cc97]196FUNCTION_BEGIN(memcpy_from_uspace)
197FUNCTION_BEGIN(memcpy_to_uspace)
[6f8a426]198 srwi. r7, r5, 3
199 addi r6, r3, -4
200 addi r4, r4, -4
[ffe276f]201 beq 2f
[6f8a426]202
203 andi. r0, r6, 3
204 mtctr r7
205 bne 5f
206
207 1:
208
[ffe276f]209 lwz r7, 4(r4)
210 lwzu r8, 8(r4)
211 stw r7, 4(r6)
212 stwu r8, 8(r6)
213 bdnz 1b
214
215 andi. r5, r5, 7
[6f8a426]216
217 2:
218
[ffe276f]219 cmplwi 0, r5, 4
220 blt 3f
221
222 lwzu r0, 4(r4)
223 addi r5, r5, -4
224 stwu r0, 4(r6)
[6f8a426]225
226 3:
227
[ffe276f]228 cmpwi 0, r5, 0
229 beqlr
230 mtctr r5
231 addi r4, r4, 3
232 addi r6, r6, 3
[6f8a426]233
234 4:
235
[ffe276f]236 lbzu r0, 1(r4)
237 stbu r0, 1(r6)
238 bdnz 4b
239 blr
[6f8a426]240
241 5:
242
[ffe276f]243 subfic r0, r0, 4
244 mtctr r0
[6f8a426]245
246 6:
247
[ffe276f]248 lbz r7, 4(r4)
249 addi r4, r4, 1
250 stb r7, 4(r6)
251 addi r6, r6, 1
252 bdnz 6b
253 subf r5, r0, r5
254 rlwinm. r7, r5, 32-3, 3, 31
255 beq 2b
256 mtctr r7
257 b 1b
[b66cc97]258FUNCTION_END(memcpy_from_uspace)
259FUNCTION_END(memcpy_to_uspace)
[e3c762cd]260
[b66cc97]261SYMBOL(memcpy_from_uspace_failover_address)
262SYMBOL(memcpy_to_uspace_failover_address)
[eedf4c5]263 /* Return zero, failure */
[ac0e791]264 xor r3, r3, r3
265 blr
[da52547]266
[b66cc97]267FUNCTION_BEGIN(early_putchar)
[da52547]268 blr
[b66cc97]269FUNCTION_END(early_putchar)
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