source: mainline/kernel/arch/ppc32/src/asm.S@ 0407636

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0407636 was f892ed3b, checked in by Martin Decky <martin@…>, 11 years ago

ppc32: remove decrementer workaround
  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/asm/regname.h>
30#include <arch/msr.h>
31#include <arch/istate_struct.h>
32
33.text
34
35.global userspace_asm
36.global iret
37.global iret_syscall
38.global memcpy_from_uspace
39.global memcpy_to_uspace
40.global memcpy_from_uspace_failover_address
41.global memcpy_to_uspace_failover_address
42.global early_putchar
43
44userspace_asm:
45
46 /*
47 * r3 = uspace_uarg
48 * r4 = stack
49 * r5 = entry
50 */
51
52 /* Disable interrupts */
53
54 mfmsr r31
55 rlwinm r31, r31, 0, 17, 15
56 mtmsr r31
57 isync
58
59 /* Set entry point */
60
61 mtsrr0 r5
62
63 /* Set privileged state, enable interrupts */
64
65 ori r31, r31, MSR_PR
66 ori r31, r31, MSR_EE
67 mtsrr1 r31
68
69 /* Set stack */
70
71 mr sp, r4
72
73 /* %r6 is defined to hold pcb_ptr - set it to 0 */
74
75 xor r6, r6, r6
76
77 /* Jump to userspace */
78
79 rfi
80
81iret:
82
83 /* Disable interrupts */
84
85 mfmsr r31
86 rlwinm r31, r31, 0, 17, 15
87 mtmsr r31
88 isync
89
90 lwz r0, ISTATE_OFFSET_R0(sp)
91 lwz r2, ISTATE_OFFSET_R2(sp)
92 lwz r3, ISTATE_OFFSET_R3(sp)
93 lwz r4, ISTATE_OFFSET_R4(sp)
94 lwz r5, ISTATE_OFFSET_R5(sp)
95 lwz r6, ISTATE_OFFSET_R6(sp)
96 lwz r7, ISTATE_OFFSET_R7(sp)
97 lwz r8, ISTATE_OFFSET_R8(sp)
98 lwz r9, ISTATE_OFFSET_R9(sp)
99 lwz r10, ISTATE_OFFSET_R10(sp)
100 lwz r11, ISTATE_OFFSET_R11(sp)
101 lwz r13, ISTATE_OFFSET_R13(sp)
102 lwz r14, ISTATE_OFFSET_R14(sp)
103 lwz r15, ISTATE_OFFSET_R15(sp)
104 lwz r16, ISTATE_OFFSET_R16(sp)
105 lwz r17, ISTATE_OFFSET_R17(sp)
106 lwz r18, ISTATE_OFFSET_R18(sp)
107 lwz r19, ISTATE_OFFSET_R19(sp)
108 lwz r20, ISTATE_OFFSET_R20(sp)
109 lwz r21, ISTATE_OFFSET_R21(sp)
110 lwz r22, ISTATE_OFFSET_R22(sp)
111 lwz r23, ISTATE_OFFSET_R23(sp)
112 lwz r24, ISTATE_OFFSET_R24(sp)
113 lwz r25, ISTATE_OFFSET_R25(sp)
114 lwz r26, ISTATE_OFFSET_R26(sp)
115 lwz r27, ISTATE_OFFSET_R27(sp)
116 lwz r28, ISTATE_OFFSET_R28(sp)
117 lwz r29, ISTATE_OFFSET_R29(sp)
118 lwz r30, ISTATE_OFFSET_R30(sp)
119 lwz r31, ISTATE_OFFSET_R31(sp)
120
121 lwz r12, ISTATE_OFFSET_CR(sp)
122 mtcr r12
123
124 lwz r12, ISTATE_OFFSET_PC(sp)
125 mtsrr0 r12
126
127 lwz r12, ISTATE_OFFSET_SRR1(sp)
128 mtsrr1 r12
129
130 lwz r12, ISTATE_OFFSET_LR(sp)
131 mtlr r12
132
133 lwz r12, ISTATE_OFFSET_CTR(sp)
134 mtctr r12
135
136 lwz r12, ISTATE_OFFSET_XER(sp)
137 mtxer r12
138
139 lwz r12, ISTATE_OFFSET_R12(sp)
140 lwz sp, ISTATE_OFFSET_SP(sp)
141
142 rfi
143
144iret_syscall:
145
146 /* Disable interrupts */
147
148 mfmsr r31
149 rlwinm r31, r31, 0, 17, 15
150 mtmsr r31
151 isync
152
153 lwz r0, ISTATE_OFFSET_R0(sp)
154 lwz r2, ISTATE_OFFSET_R2(sp)
155 lwz r4, ISTATE_OFFSET_R4(sp)
156 lwz r5, ISTATE_OFFSET_R5(sp)
157 lwz r6, ISTATE_OFFSET_R6(sp)
158 lwz r7, ISTATE_OFFSET_R7(sp)
159 lwz r8, ISTATE_OFFSET_R8(sp)
160 lwz r9, ISTATE_OFFSET_R9(sp)
161 lwz r10, ISTATE_OFFSET_R10(sp)
162 lwz r11, ISTATE_OFFSET_R11(sp)
163 lwz r13, ISTATE_OFFSET_R13(sp)
164 lwz r14, ISTATE_OFFSET_R14(sp)
165 lwz r15, ISTATE_OFFSET_R15(sp)
166 lwz r16, ISTATE_OFFSET_R16(sp)
167 lwz r17, ISTATE_OFFSET_R17(sp)
168 lwz r18, ISTATE_OFFSET_R18(sp)
169 lwz r19, ISTATE_OFFSET_R19(sp)
170 lwz r20, ISTATE_OFFSET_R20(sp)
171 lwz r21, ISTATE_OFFSET_R21(sp)
172 lwz r22, ISTATE_OFFSET_R22(sp)
173 lwz r23, ISTATE_OFFSET_R23(sp)
174 lwz r24, ISTATE_OFFSET_R24(sp)
175 lwz r25, ISTATE_OFFSET_R25(sp)
176 lwz r26, ISTATE_OFFSET_R26(sp)
177 lwz r27, ISTATE_OFFSET_R27(sp)
178 lwz r28, ISTATE_OFFSET_R28(sp)
179 lwz r29, ISTATE_OFFSET_R29(sp)
180 lwz r30, ISTATE_OFFSET_R30(sp)
181 lwz r31, ISTATE_OFFSET_R31(sp)
182
183 lwz r12, ISTATE_OFFSET_CR(sp)
184 mtcr r12
185
186 lwz r12, ISTATE_OFFSET_PC(sp)
187 mtsrr0 r12
188
189 lwz r12, ISTATE_OFFSET_SRR1(sp)
190 mtsrr1 r12
191
192 lwz r12, ISTATE_OFFSET_LR(sp)
193 mtlr r12
194
195 lwz r12, ISTATE_OFFSET_CTR(sp)
196 mtctr r12
197
198 lwz r12, ISTATE_OFFSET_XER(sp)
199 mtxer r12
200
201 lwz r12, ISTATE_OFFSET_R12(sp)
202 lwz sp, ISTATE_OFFSET_SP(sp)
203
204 rfi
205
206memcpy_from_uspace:
207memcpy_to_uspace:
208
209 srwi. r7, r5, 3
210 addi r6, r3, -4
211 addi r4, r4, -4
212 beq 2f
213
214 andi. r0, r6, 3
215 mtctr r7
216 bne 5f
217
218 1:
219
220 lwz r7, 4(r4)
221 lwzu r8, 8(r4)
222 stw r7, 4(r6)
223 stwu r8, 8(r6)
224 bdnz 1b
225
226 andi. r5, r5, 7
227
228 2:
229
230 cmplwi 0, r5, 4
231 blt 3f
232
233 lwzu r0, 4(r4)
234 addi r5, r5, -4
235 stwu r0, 4(r6)
236
237 3:
238
239 cmpwi 0, r5, 0
240 beqlr
241 mtctr r5
242 addi r4, r4, 3
243 addi r6, r6, 3
244
245 4:
246
247 lbzu r0, 1(r4)
248 stbu r0, 1(r6)
249 bdnz 4b
250 blr
251
252 5:
253
254 subfic r0, r0, 4
255 mtctr r0
256
257 6:
258
259 lbz r7, 4(r4)
260 addi r4, r4, 1
261 stb r7, 4(r6)
262 addi r6, r6, 1
263 bdnz 6b
264 subf r5, r0, r5
265 rlwinm. r7, r5, 32-3, 3, 31
266 beq 2b
267 mtctr r7
268 b 1b
269
270memcpy_from_uspace_failover_address:
271memcpy_to_uspace_failover_address:
272 /* Return zero, failure */
273 xor r3, r3, r3
274 blr
275
276early_putchar:
277 blr
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