[eedf4c5] | 1 | /*
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| 2 | * Copyright (c) 2005 Martin Decky
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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[efa9b73] | 28 |
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[b66cc97] | 29 | #include <abi/asmtool.h>
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[37c8975] | 30 | #include <arch/asm/regname.h>
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[c0699467] | 31 | #include <arch/msr.h>
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[beb16cfa] | 32 | #include <arch/istate_struct.h>
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[10caad0] | 33 |
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[efa9b73] | 34 | .text
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| 35 |
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[b66cc97] | 36 | FUNCTION_BEGIN(userspace_asm)
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[eedf4c5] | 37 | /*
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| 38 | * r3 = uspace_uarg
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| 39 | * r4 = stack
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| 40 | * r5 = entry
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| 41 | */
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[a35b458] | 42 |
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[eedf4c5] | 43 | /* Disable interrupts */
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[a35b458] | 44 |
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[e692a27] | 45 | mfmsr r31
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| 46 | rlwinm r31, r31, 0, 17, 15
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| 47 | mtmsr r31
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[5a42886] | 48 | isync
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[a35b458] | 49 |
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[eedf4c5] | 50 | /* Set entry point */
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[a35b458] | 51 |
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[e692a27] | 52 | mtsrr0 r5
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[a35b458] | 53 |
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[52c0b8c] | 54 | /* Set privileged state, enable interrupts */
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[a35b458] | 55 |
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[ffe276f] | 56 | ori r31, r31, MSR_PR
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| 57 | ori r31, r31, MSR_EE
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[e692a27] | 58 | mtsrr1 r31
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[a35b458] | 59 |
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[eedf4c5] | 60 | /* Set stack */
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[a35b458] | 61 |
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[e692a27] | 62 | mr sp, r4
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[a35b458] | 63 |
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[eedf4c5] | 64 | /* %r6 is defined to hold pcb_ptr - set it to 0 */
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[a35b458] | 65 |
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[c1b455e] | 66 | xor r6, r6, r6
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[a35b458] | 67 |
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[eedf4c5] | 68 | /* Jump to userspace */
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[a35b458] | 69 |
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[e692a27] | 70 | rfi
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[b66cc97] | 71 | FUNCTION_END(userspace_asm)
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[e692a27] | 72 |
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[b66cc97] | 73 | SYMBOL(iret)
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[eedf4c5] | 74 | /* Disable interrupts */
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[a35b458] | 75 |
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[e34a141] | 76 | mfmsr r31
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| 77 | rlwinm r31, r31, 0, 17, 15
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| 78 | mtmsr r31
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[5a42886] | 79 | isync
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[a35b458] | 80 |
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[beb16cfa] | 81 | lwz r0, ISTATE_OFFSET_R0(sp)
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| 82 | lwz r2, ISTATE_OFFSET_R2(sp)
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| 83 | lwz r3, ISTATE_OFFSET_R3(sp)
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| 84 | lwz r4, ISTATE_OFFSET_R4(sp)
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| 85 | lwz r5, ISTATE_OFFSET_R5(sp)
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| 86 | lwz r6, ISTATE_OFFSET_R6(sp)
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| 87 | lwz r7, ISTATE_OFFSET_R7(sp)
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| 88 | lwz r8, ISTATE_OFFSET_R8(sp)
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| 89 | lwz r9, ISTATE_OFFSET_R9(sp)
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| 90 | lwz r10, ISTATE_OFFSET_R10(sp)
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| 91 | lwz r11, ISTATE_OFFSET_R11(sp)
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| 92 | lwz r13, ISTATE_OFFSET_R13(sp)
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| 93 | lwz r14, ISTATE_OFFSET_R14(sp)
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| 94 | lwz r15, ISTATE_OFFSET_R15(sp)
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| 95 | lwz r16, ISTATE_OFFSET_R16(sp)
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| 96 | lwz r17, ISTATE_OFFSET_R17(sp)
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| 97 | lwz r18, ISTATE_OFFSET_R18(sp)
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| 98 | lwz r19, ISTATE_OFFSET_R19(sp)
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| 99 | lwz r20, ISTATE_OFFSET_R20(sp)
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| 100 | lwz r21, ISTATE_OFFSET_R21(sp)
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| 101 | lwz r22, ISTATE_OFFSET_R22(sp)
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| 102 | lwz r23, ISTATE_OFFSET_R23(sp)
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| 103 | lwz r24, ISTATE_OFFSET_R24(sp)
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| 104 | lwz r25, ISTATE_OFFSET_R25(sp)
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| 105 | lwz r26, ISTATE_OFFSET_R26(sp)
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| 106 | lwz r27, ISTATE_OFFSET_R27(sp)
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| 107 | lwz r28, ISTATE_OFFSET_R28(sp)
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| 108 | lwz r29, ISTATE_OFFSET_R29(sp)
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| 109 | lwz r30, ISTATE_OFFSET_R30(sp)
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| 110 | lwz r31, ISTATE_OFFSET_R31(sp)
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[a35b458] | 111 |
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[beb16cfa] | 112 | lwz r12, ISTATE_OFFSET_CR(sp)
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[e34a141] | 113 | mtcr r12
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[a35b458] | 114 |
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[beb16cfa] | 115 | lwz r12, ISTATE_OFFSET_PC(sp)
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[e34a141] | 116 | mtsrr0 r12
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[a35b458] | 117 |
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[beb16cfa] | 118 | lwz r12, ISTATE_OFFSET_SRR1(sp)
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[e34a141] | 119 | mtsrr1 r12
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[a35b458] | 120 |
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[beb16cfa] | 121 | lwz r12, ISTATE_OFFSET_LR(sp)
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[e34a141] | 122 | mtlr r12
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[a35b458] | 123 |
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[beb16cfa] | 124 | lwz r12, ISTATE_OFFSET_CTR(sp)
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[762a824] | 125 | mtctr r12
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[a35b458] | 126 |
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[beb16cfa] | 127 | lwz r12, ISTATE_OFFSET_XER(sp)
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[762a824] | 128 | mtxer r12
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[a35b458] | 129 |
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[beb16cfa] | 130 | lwz r12, ISTATE_OFFSET_R12(sp)
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| 131 | lwz sp, ISTATE_OFFSET_SP(sp)
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[a35b458] | 132 |
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[e34a141] | 133 | rfi
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[762a824] | 134 |
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[b66cc97] | 135 | SYMBOL(iret_syscall)
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[eedf4c5] | 136 | /* Disable interrupts */
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[a35b458] | 137 |
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[e34a141] | 138 | mfmsr r31
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| 139 | rlwinm r31, r31, 0, 17, 15
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| 140 | mtmsr r31
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[5a42886] | 141 | isync
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[a35b458] | 142 |
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[beb16cfa] | 143 | lwz r0, ISTATE_OFFSET_R0(sp)
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| 144 | lwz r2, ISTATE_OFFSET_R2(sp)
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| 145 | lwz r4, ISTATE_OFFSET_R4(sp)
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| 146 | lwz r5, ISTATE_OFFSET_R5(sp)
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| 147 | lwz r6, ISTATE_OFFSET_R6(sp)
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| 148 | lwz r7, ISTATE_OFFSET_R7(sp)
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| 149 | lwz r8, ISTATE_OFFSET_R8(sp)
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| 150 | lwz r9, ISTATE_OFFSET_R9(sp)
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| 151 | lwz r10, ISTATE_OFFSET_R10(sp)
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| 152 | lwz r11, ISTATE_OFFSET_R11(sp)
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| 153 | lwz r13, ISTATE_OFFSET_R13(sp)
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| 154 | lwz r14, ISTATE_OFFSET_R14(sp)
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| 155 | lwz r15, ISTATE_OFFSET_R15(sp)
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| 156 | lwz r16, ISTATE_OFFSET_R16(sp)
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| 157 | lwz r17, ISTATE_OFFSET_R17(sp)
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| 158 | lwz r18, ISTATE_OFFSET_R18(sp)
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| 159 | lwz r19, ISTATE_OFFSET_R19(sp)
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| 160 | lwz r20, ISTATE_OFFSET_R20(sp)
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| 161 | lwz r21, ISTATE_OFFSET_R21(sp)
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| 162 | lwz r22, ISTATE_OFFSET_R22(sp)
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| 163 | lwz r23, ISTATE_OFFSET_R23(sp)
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| 164 | lwz r24, ISTATE_OFFSET_R24(sp)
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| 165 | lwz r25, ISTATE_OFFSET_R25(sp)
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| 166 | lwz r26, ISTATE_OFFSET_R26(sp)
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| 167 | lwz r27, ISTATE_OFFSET_R27(sp)
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| 168 | lwz r28, ISTATE_OFFSET_R28(sp)
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| 169 | lwz r29, ISTATE_OFFSET_R29(sp)
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| 170 | lwz r30, ISTATE_OFFSET_R30(sp)
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| 171 | lwz r31, ISTATE_OFFSET_R31(sp)
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[a35b458] | 172 |
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[beb16cfa] | 173 | lwz r12, ISTATE_OFFSET_CR(sp)
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[e34a141] | 174 | mtcr r12
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[a35b458] | 175 |
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[beb16cfa] | 176 | lwz r12, ISTATE_OFFSET_PC(sp)
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[e34a141] | 177 | mtsrr0 r12
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[a35b458] | 178 |
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[beb16cfa] | 179 | lwz r12, ISTATE_OFFSET_SRR1(sp)
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[e34a141] | 180 | mtsrr1 r12
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[a35b458] | 181 |
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[beb16cfa] | 182 | lwz r12, ISTATE_OFFSET_LR(sp)
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[e34a141] | 183 | mtlr r12
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[a35b458] | 184 |
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[beb16cfa] | 185 | lwz r12, ISTATE_OFFSET_CTR(sp)
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[e34a141] | 186 | mtctr r12
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[a35b458] | 187 |
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[beb16cfa] | 188 | lwz r12, ISTATE_OFFSET_XER(sp)
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[e34a141] | 189 | mtxer r12
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[a35b458] | 190 |
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[beb16cfa] | 191 | lwz r12, ISTATE_OFFSET_R12(sp)
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| 192 | lwz sp, ISTATE_OFFSET_SP(sp)
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[a35b458] | 193 |
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[91d5ad6] | 194 | rfi
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[b60c582] | 195 |
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[b66cc97] | 196 | FUNCTION_BEGIN(memcpy_from_uspace)
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| 197 | FUNCTION_BEGIN(memcpy_to_uspace)
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[6f8a426] | 198 | srwi. r7, r5, 3
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| 199 | addi r6, r3, -4
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| 200 | addi r4, r4, -4
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[ffe276f] | 201 | beq 2f
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[a35b458] | 202 |
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[6f8a426] | 203 | andi. r0, r6, 3
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| 204 | mtctr r7
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| 205 | bne 5f
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[a35b458] | 206 |
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[6f8a426] | 207 | 1:
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[a35b458] | 208 |
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[ffe276f] | 209 | lwz r7, 4(r4)
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| 210 | lwzu r8, 8(r4)
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| 211 | stw r7, 4(r6)
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| 212 | stwu r8, 8(r6)
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| 213 | bdnz 1b
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[a35b458] | 214 |
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[ffe276f] | 215 | andi. r5, r5, 7
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[a35b458] | 216 |
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[6f8a426] | 217 | 2:
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[a35b458] | 218 |
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[ffe276f] | 219 | cmplwi 0, r5, 4
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| 220 | blt 3f
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[a35b458] | 221 |
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[ffe276f] | 222 | lwzu r0, 4(r4)
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| 223 | addi r5, r5, -4
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| 224 | stwu r0, 4(r6)
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[a35b458] | 225 |
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[6f8a426] | 226 | 3:
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[a35b458] | 227 |
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[ffe276f] | 228 | cmpwi 0, r5, 0
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| 229 | beqlr
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| 230 | mtctr r5
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| 231 | addi r4, r4, 3
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| 232 | addi r6, r6, 3
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[a35b458] | 233 |
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[6f8a426] | 234 | 4:
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[a35b458] | 235 |
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[ffe276f] | 236 | lbzu r0, 1(r4)
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| 237 | stbu r0, 1(r6)
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| 238 | bdnz 4b
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| 239 | blr
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[a35b458] | 240 |
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[6f8a426] | 241 | 5:
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[a35b458] | 242 |
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[ffe276f] | 243 | subfic r0, r0, 4
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| 244 | mtctr r0
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[a35b458] | 245 |
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[6f8a426] | 246 | 6:
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[a35b458] | 247 |
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[ffe276f] | 248 | lbz r7, 4(r4)
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| 249 | addi r4, r4, 1
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| 250 | stb r7, 4(r6)
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| 251 | addi r6, r6, 1
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| 252 | bdnz 6b
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| 253 | subf r5, r0, r5
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| 254 | rlwinm. r7, r5, 32-3, 3, 31
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| 255 | beq 2b
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| 256 | mtctr r7
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| 257 | b 1b
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[b66cc97] | 258 | FUNCTION_END(memcpy_from_uspace)
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| 259 | FUNCTION_END(memcpy_to_uspace)
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[e3c762cd] | 260 |
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[b66cc97] | 261 | SYMBOL(memcpy_from_uspace_failover_address)
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| 262 | SYMBOL(memcpy_to_uspace_failover_address)
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[eedf4c5] | 263 | /* Return zero, failure */
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[ac0e791] | 264 | xor r3, r3, r3
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| 265 | blr
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[da52547] | 266 |
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[28a5ebd] | 267 | FUNCTION_BEGIN(early_putuchar)
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[da52547] | 268 | blr
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[28a5ebd] | 269 | FUNCTION_END(early_putuchar)
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