| [f761f1eb] | 1 | /*
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| [df4ed85] | 2 | * Copyright (c) 2005 Martin Decky
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| [f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| [1bb2e7a] | 29 | /** @addtogroup ppc32
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| [b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| [06e1e95] | 35 | #ifndef KERN_ppc32_CPU_H_
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| 36 | #define KERN_ppc32_CPU_H_
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| [04b1b8a] | 37 |
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| [3500f75] | 38 | /* MSR bits */
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| 39 | #define MSR_DR (1 << 4)
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| 40 | #define MSR_IR (1 << 5)
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| 41 | #define MSR_PR (1 << 14)
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| 42 | #define MSR_EE (1 << 15)
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| 43 |
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| 44 | /* HID0 bits */
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| 45 | #define HID0_STEN (1 << 24)
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| 46 | #define HID0_ICE (1 << 15)
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| 47 | #define HID0_DCE (1 << 14)
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| 48 | #define HID0_ICFI (1 << 11)
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| 49 | #define HID0_DCI (1 << 10)
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| 50 |
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| 51 | #ifndef __ASM__
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| 52 |
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| 53 | #include <typedefs.h>
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| [7a0359b] | 54 | #include <trace.h>
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| [04b1b8a] | 55 |
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| [f429331] | 56 | typedef struct {
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| [3500f75] | 57 | uint16_t version;
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| 58 | uint16_t revision;
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| 59 | } __attribute__ ((packed)) cpu_arch_t;
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| 60 |
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| [7a0359b] | 61 | NO_TRACE static inline void cpu_version(cpu_arch_t *info)
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| [3500f75] | 62 | {
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| 63 | asm volatile (
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| 64 | "mfpvr %[cpu_info]\n"
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| 65 | : [cpu_info] "=r" (*info)
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| 66 | );
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| 67 | }
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| 68 |
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| 69 | #endif /* __ASM__ */
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| 70 |
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| [04b1b8a] | 71 | #endif
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| [b45c443] | 72 |
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| [1bb2e7a] | 73 | /** @}
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| [b45c443] | 74 | */
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