source: mainline/kernel/arch/ppc32/include/cpu.h@ e2ea4ab1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e2ea4ab1 was 3500f75, checked in by Martin Decky <martin@…>, 15 years ago

ppc32: add interrupts_disabled(), simplify CPU identification

  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ppc32
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ppc32_CPU_H_
36#define KERN_ppc32_CPU_H_
37
38/* MSR bits */
39#define MSR_DR (1 << 4)
40#define MSR_IR (1 << 5)
41#define MSR_PR (1 << 14)
42#define MSR_EE (1 << 15)
43
44/* HID0 bits */
45#define HID0_STEN (1 << 24)
46#define HID0_ICE (1 << 15)
47#define HID0_DCE (1 << 14)
48#define HID0_ICFI (1 << 11)
49#define HID0_DCI (1 << 10)
50
51#ifndef __ASM__
52
53#include <typedefs.h>
54
55typedef struct {
56 uint16_t version;
57 uint16_t revision;
58} __attribute__ ((packed)) cpu_arch_t;
59
60static inline void cpu_version(cpu_arch_t *info)
61{
62 asm volatile (
63 "mfpvr %[cpu_info]\n"
64 : [cpu_info] "=r" (*info)
65 );
66}
67
68#endif /* __ASM__ */
69
70#endif
71
72/** @}
73 */
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