| [2429e4a] | 1 | #
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| 2 | # Copyright (c) 2003-2004 Jakub Jermar
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #include <arch/asm/regname.h>
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| 30 | #include <arch/mm/page.h>
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| 31 | #include <arch/asm/boot.h>
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| 32 | #include <arch/context_offset.h>
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| 33 | #include <arch/stack.h>
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| 34 |
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| 35 | .text
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| 36 |
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| 37 | .set noat
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| 38 | .set noreorder
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| 39 | .set nomacro
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| 40 |
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| 41 | .global kernel_image_start
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| 42 | .global tlb_refill_entry
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| 43 | .global cache_error_entry
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| 44 | .global exception_entry
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| 45 | .global userspace_asm
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| 46 |
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| 47 | /*
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| 48 | * Which status bits are thread-local:
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| 49 | * KSU(UM), EXL, ERL, IE
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| 50 | */
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| 51 | #define REG_SAVE_MASK 0x1f
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| 52 |
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| 53 | #define ISTATE_OFFSET_A0 0
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| 54 | #define ISTATE_OFFSET_A1 8
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| 55 | #define ISTATE_OFFSET_A2 16
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| 56 | #define ISTATE_OFFSET_A3 24
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| 57 | #define ISTATE_OFFSET_T0 32
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| 58 | #define ISTATE_OFFSET_T1 40
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| 59 | #define ISTATE_OFFSET_V0 48
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| 60 | #define ISTATE_OFFSET_V1 56
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| 61 | #define ISTATE_OFFSET_AT 64
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| 62 | #define ISTATE_OFFSET_T2 72
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| 63 | #define ISTATE_OFFSET_T3 80
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| 64 | #define ISTATE_OFFSET_T4 88
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| 65 | #define ISTATE_OFFSET_T5 96
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| 66 | #define ISTATE_OFFSET_T6 104
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| 67 | #define ISTATE_OFFSET_T7 112
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| 68 | #define ISTATE_OFFSET_S0 120
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| 69 | #define ISTATE_OFFSET_S1 128
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| 70 | #define ISTATE_OFFSET_S2 136
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| 71 | #define ISTATE_OFFSET_S3 144
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| 72 | #define ISTATE_OFFSET_S4 152
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| 73 | #define ISTATE_OFFSET_S5 160
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| 74 | #define ISTATE_OFFSET_S6 168
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| 75 | #define ISTATE_OFFSET_S7 176
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| 76 | #define ISTATE_OFFSET_T8 184
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| 77 | #define ISTATE_OFFSET_T9 192
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| 78 | #define ISTATE_OFFSET_KT0 200
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| 79 | #define ISTATE_OFFSET_KT1 208
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| 80 | #define ISTATE_OFFSET_GP 216
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| 81 | #define ISTATE_OFFSET_SP 224
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| 82 | #define ISTATE_OFFSET_S8 232
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| 83 | #define ISTATE_OFFSET_RA 240
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| 84 | #define ISTATE_OFFSET_LO 248
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| 85 | #define ISTATE_OFFSET_HI 252
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| 86 | #define ISTATE_OFFSET_STATUS 256
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| 87 | #define ISTATE_OFFSET_EPC 264
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| 88 | #define ISTATE_OFFSET_ALIGNMENT 272
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| 89 |
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| 90 | #define ISTATE_SOFT_SIZE 280
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| 91 |
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| 92 | /*
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| 93 | * The fake ABI prologue is never executed and may not be part of the
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| 94 | * procedure's body. Instead, it should be immediately preceding the procedure's
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| 95 | * body. Its only purpose is to trick the stack trace walker into thinking that
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| 96 | * the exception is more or less just a normal function call.
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| 97 | */
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| 98 | .macro FAKE_ABI_PROLOGUE
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| 99 | sub $sp, ISTATE_SOFT_SIZE
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| 100 | sd $ra, ISTATE_OFFSET_EPC($sp)
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| 101 | .endm
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| 102 |
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| 103 | /*
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| 104 | * Save registers to space defined by \r
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| 105 | * We will change status: Disable ERL, EXL, UM, IE
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| 106 | * These changes will be automatically reversed in REGISTER_LOAD
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| 107 | * %sp is NOT saved as part of these registers
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| 108 | */
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| 109 | .macro REGISTERS_STORE_AND_EXC_RESET r
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| 110 | sd $at, ISTATE_OFFSET_AT(\r)
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| 111 | sd $v0, ISTATE_OFFSET_V0(\r)
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| 112 | sd $v1, ISTATE_OFFSET_V1(\r)
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| 113 | sd $a0, ISTATE_OFFSET_A0(\r)
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| 114 | sd $a1, ISTATE_OFFSET_A1(\r)
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| 115 | sd $a2, ISTATE_OFFSET_A2(\r)
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| 116 | sd $a3, ISTATE_OFFSET_A3(\r)
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| 117 | sd $t0, ISTATE_OFFSET_T0(\r)
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| 118 | sd $t1, ISTATE_OFFSET_T1(\r)
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| 119 | sd $t2, ISTATE_OFFSET_T2(\r)
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| 120 | sd $t3, ISTATE_OFFSET_T3(\r)
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| 121 | sd $t4, ISTATE_OFFSET_T4(\r)
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| 122 | sd $t5, ISTATE_OFFSET_T5(\r)
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| 123 | sd $t6, ISTATE_OFFSET_T6(\r)
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| 124 | sd $t7, ISTATE_OFFSET_T7(\r)
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| 125 | sd $t8, ISTATE_OFFSET_T8(\r)
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| 126 | sd $t9, ISTATE_OFFSET_T9(\r)
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| 127 | sd $s0, ISTATE_OFFSET_S0(\r)
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| 128 | sd $s1, ISTATE_OFFSET_S1(\r)
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| 129 | sd $s2, ISTATE_OFFSET_S2(\r)
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| 130 | sd $s3, ISTATE_OFFSET_S3(\r)
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| 131 | sd $s4, ISTATE_OFFSET_S4(\r)
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| 132 | sd $s5, ISTATE_OFFSET_S5(\r)
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| 133 | sd $s6, ISTATE_OFFSET_S6(\r)
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| 134 | sd $s7, ISTATE_OFFSET_S7(\r)
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| 135 | sd $s8, ISTATE_OFFSET_S8(\r)
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| 136 |
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| 137 | mflo $at
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| 138 | sw $at, ISTATE_OFFSET_LO(\r)
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| 139 | mfhi $at
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| 140 | sw $at, ISTATE_OFFSET_HI(\r)
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| 141 |
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| 142 | sd $gp, ISTATE_OFFSET_GP(\r)
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| 143 | sd $ra, ISTATE_OFFSET_RA(\r)
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| 144 | sd $k0, ISTATE_OFFSET_KT0(\r)
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| 145 | sd $k1, ISTATE_OFFSET_KT1(\r)
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| 146 |
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| 147 | dmfc0 $t0, $status
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| 148 | dmfc0 $t1, $epc
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| 149 |
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| 150 | /* save only KSU, EXL, ERL, IE */
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| 151 | and $t2, $t0, REG_SAVE_MASK
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| 152 |
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| 153 | /* clear KSU, EXL, ERL, IE */
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| 154 | li $t3, ~(REG_SAVE_MASK)
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| 155 | and $t0, $t0, $t3
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| 156 |
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| 157 | sd $t2, ISTATE_OFFSET_STATUS(\r)
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| 158 | sd $t1, ISTATE_OFFSET_EPC(\r)
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| 159 | dmtc0 $t0, $status
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| 160 | .endm
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| 161 |
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| 162 | .macro REGISTERS_LOAD r
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| 163 | /*
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| 164 | * Update only UM, EXR, IE from status, the rest
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| 165 | * is controlled by OS and not bound to task.
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| 166 | */
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| 167 | dmfc0 $t0, $status
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| 168 | ld $t1, ISTATE_OFFSET_STATUS(\r)
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| 169 |
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| 170 | /* mask UM, EXL, ERL, IE */
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| 171 | li $t2, ~REG_SAVE_MASK
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| 172 | and $t0, $t0, $t2
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| 173 |
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| 174 | /* copy UM, EXL, ERL, IE from saved status */
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| 175 | or $t0, $t0, $t1
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| 176 | dmtc0 $t0, $status
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| 177 |
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| 178 | ld $v0, ISTATE_OFFSET_V0(\r)
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| 179 | ld $v1, ISTATE_OFFSET_V1(\r)
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| 180 | ld $a0, ISTATE_OFFSET_A0(\r)
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| 181 | ld $a1, ISTATE_OFFSET_A1(\r)
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| 182 | ld $a2, ISTATE_OFFSET_A2(\r)
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| 183 | ld $a3, ISTATE_OFFSET_A3(\r)
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| 184 | ld $t0, ISTATE_OFFSET_T0(\r)
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| 185 | ld $t1, ISTATE_OFFSET_T1(\r)
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| 186 | ld $t2, ISTATE_OFFSET_T2(\r)
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| 187 | ld $t3, ISTATE_OFFSET_T3(\r)
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| 188 | ld $t4, ISTATE_OFFSET_T4(\r)
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| 189 | ld $t5, ISTATE_OFFSET_T5(\r)
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| 190 | ld $t6, ISTATE_OFFSET_T6(\r)
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| 191 | ld $t7, ISTATE_OFFSET_T7(\r)
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| 192 | ld $t8, ISTATE_OFFSET_T8(\r)
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| 193 | ld $t9, ISTATE_OFFSET_T9(\r)
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| 194 |
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| 195 | ld $gp, ISTATE_OFFSET_GP(\r)
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| 196 | ld $ra, ISTATE_OFFSET_RA(\r)
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| 197 | ld $k1, ISTATE_OFFSET_KT1(\r)
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| 198 |
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| 199 | lw $at, ISTATE_OFFSET_LO(\r)
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| 200 | mtlo $at
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| 201 | lw $at, ISTATE_OFFSET_HI(\r)
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| 202 | mthi $at
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| 203 |
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| 204 | ld $at, ISTATE_OFFSET_EPC(\r)
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| 205 | dmtc0 $at, $epc
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| 206 |
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| 207 | ld $at, ISTATE_OFFSET_AT(\r)
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| 208 | ld $sp, ISTATE_OFFSET_SP(\r)
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| 209 | .endm
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| 210 |
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| 211 | /*
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| 212 | * Move kernel stack pointer address to register $k0.
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| 213 | * If we are in user mode, load the appropriate stack address.
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| 214 | */
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| 215 | .macro KERNEL_STACK_TO_K0
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| 216 | /* if we are in user mode */
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| 217 | dmfc0 $k0, $status
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| 218 | andi $k0, 0x10
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| 219 |
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| 220 | beq $k0, $0, 1f
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| 221 | move $k0, $sp
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| 222 |
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| 223 | /* move $k0 pointer to kernel stack */
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| 224 | dla $k0, supervisor_sp
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| 225 |
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| 226 | /* move $k0 (supervisor_sp) */
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| 227 | lw $k0, ($k0)
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| 228 |
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| 229 | 1:
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| 230 | .endm
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| 231 |
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| 232 | .org 0x0
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| 233 | kernel_image_start:
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| 234 | /* load temporary stack */
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| 235 | lui $sp, %hi(end_stack)
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| 236 | ori $sp, $sp, %lo(end_stack)
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| 237 |
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| 238 | /* not sure about this, but might be needed for PIC code */
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| 239 | lui $gp, 0x8000
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| 240 |
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| 241 | /* $a1 contains physical address of bootinfo_t */
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| 242 | jal arch_pre_main
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| 243 | nop
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| 244 |
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| 245 | j main_bsp
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| 246 | nop
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| 247 |
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| 248 | .space TEMP_STACK_SIZE
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| 249 | end_stack:
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| 250 |
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| 251 | tlb_refill_entry:
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| 252 | j tlb_refill_handler
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| 253 | nop
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| 254 |
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| 255 | cache_error_entry:
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| 256 | j cache_error_handler
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| 257 | nop
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| 258 |
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| 259 | exception_entry:
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| 260 | j exception_handler
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| 261 | nop
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| 262 |
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| 263 | FAKE_ABI_PROLOGUE
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| 264 | exception_handler:
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| 265 | KERNEL_STACK_TO_K0
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| 266 |
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| 267 | sub $k0, ISTATE_SOFT_SIZE
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| 268 | sw $sp, ISTATE_OFFSET_SP($k0)
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| 269 | move $sp, $k0
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| 270 |
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| 271 | mfc0 $k0, $cause
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| 272 |
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| 273 | sra $k0, $k0, 0x2 /* cp0_exc_cause() part 1 */
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| 274 | andi $k0, $k0, 0x1f /* cp0_exc_cause() part 2 */
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| 275 | sub $k0, 8 /* 8 = SYSCALL */
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| 276 |
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| 277 | beqz $k0, syscall_shortcut
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| 278 | add $k0, 8 /* revert $k0 back to correct exc number */
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| 279 |
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| 280 | REGISTERS_STORE_AND_EXC_RESET $sp
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| 281 |
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| 282 | move $a1, $sp
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| 283 | jal exc_dispatch /* exc_dispatch(excno, register_space) */
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| 284 | move $a0, $k0
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| 285 |
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| 286 | REGISTERS_LOAD $sp
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| 287 | /* the $sp is automatically restored to former value */
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| 288 | eret
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| 289 |
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| 290 | /** Syscall entry
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| 291 | *
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| 292 | * Registers:
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| 293 | *
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| 294 | * @param $v0 Syscall number.
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| 295 | * @param $a0 1st argument.
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| 296 | * @param $a1 2nd argument.
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| 297 | * @param $a2 3rd argument.
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| 298 | * @param $a3 4th argument.
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| 299 | * @param $t0 5th argument.
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| 300 | * @param $t1 6th argument.
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| 301 | *
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| 302 | * @return The return value will be stored in $v0.
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| 303 | *
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| 304 | */
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| 305 | syscall_shortcut:
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| 306 | mfc0 $t3, $epc
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| 307 | mfc0 $t2, $status
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| 308 | sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */
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| 309 | sw $k1, ISTATE_OFFSET_KT1($sp) /* save $k1 not saved on context switch */
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| 310 |
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| 311 | and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */
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| 312 | li $t5, ~(0x1f)
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| 313 | and $t2, $t2, $t5 /* clear KSU, EXL, ERL */
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| 314 | ori $t2, $t2, 0x1 /* set IE */
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| 315 |
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| 316 | sw $t4, ISTATE_OFFSET_STATUS($sp)
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| 317 | mtc0 $t2, $status
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| 318 |
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| 319 | /*
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| 320 | * Call the higher level system call handler.
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| 321 | *
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| 322 | */
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| 323 | sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */
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| 324 | sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */
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| 325 | jal syscall_handler
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| 326 | sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */
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| 327 |
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| 328 | /* restore status */
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| 329 | mfc0 $t2, $status
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| 330 | lw $t3, ISTATE_OFFSET_STATUS($sp)
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| 331 |
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| 332 | /*
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| 333 | * Change back to EXL = 1 (from last exception), otherwise
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| 334 | * an interrupt could rewrite the CP0 - EPC.
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| 335 | *
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| 336 | */
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| 337 | li $t4, ~REG_SAVE_MASK /* mask UM, EXL, ERL, IE */
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| 338 | and $t2, $t2, $t4
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| 339 | or $t2, $t2, $t3 /* copy saved UM, EXL, ERL, IE */
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| 340 | mtc0 $t2, $status
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| 341 |
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| 342 | /* restore epc + 4 */
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| 343 | lw $t2, ISTATE_OFFSET_EPC($sp)
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| 344 | lw $k1, ISTATE_OFFSET_KT1($sp)
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| 345 | addi $t2, $t2, 4
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| 346 | mtc0 $t2, $epc
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| 347 |
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| 348 | lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */
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| 349 | eret
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| 350 |
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| 351 | FAKE_ABI_PROLOGUE
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| 352 | tlb_refill_handler:
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| 353 | KERNEL_STACK_TO_K0
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| 354 | sub $k0, ISTATE_SOFT_SIZE
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| 355 | REGISTERS_STORE_AND_EXC_RESET $k0
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| 356 | sw $sp, ISTATE_OFFSET_SP($k0)
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| 357 | move $sp, $k0
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| 358 |
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| 359 | jal tlb_refill
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| 360 | move $a0, $sp
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| 361 |
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| 362 | REGISTERS_LOAD $sp
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| 363 | eret
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| 364 |
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| 365 | FAKE_ABI_PROLOGUE
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| 366 | cache_error_handler:
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| 367 | KERNEL_STACK_TO_K0
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| 368 | sub $k0, ISTATE_SOFT_SIZE
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| 369 | REGISTERS_STORE_AND_EXC_RESET $k0
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| 370 | sw $sp, ISTATE_OFFSET_SP($k0)
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| 371 | move $sp, $k0
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| 372 |
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| 373 | jal cache_error
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| 374 | move $a0, $sp
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| 375 |
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| 376 | REGISTERS_LOAD $sp
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| 377 | eret
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| 378 |
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| 379 | userspace_asm:
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| 380 | move $sp, $a0
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| 381 | move $v0, $a1
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| 382 | move $t9, $a2 /* set up correct entry into PIC code */
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| 383 | xor $a0, $a0, $a0 /* $a0 is defined to hold pcb_ptr */
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| 384 | /* set it to 0 */
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| 385 | eret
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