source: mainline/kernel/arch/mips32/src/mips32.c@ aca97582

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since aca97582 was d86393c8, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 6 years ago

The variable supervisor_sp doesn't have to be in .text section

  • Property mode set to 100644
File size: 5.8 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[c5429fe]29/** @addtogroup kernel_mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch.h>
[36df4109]36#include <arch/arch.h>
[d8db519]37#include <typedefs.h>
38#include <errno.h>
39#include <interrupt.h>
40#include <macros.h>
41#include <str.h>
[44a7ee5]42#include <mem.h>
[d8db519]43#include <userspace.h>
[76d0981d]44#include <stdbool.h>
[281b607]45#include <syscall/syscall.h>
[06a583e]46#include <sysinfo/sysinfo.h>
[d8db519]47#include <arch/debug.h>
[5bb8e45]48#include <arch/debugger.h>
[ae7ba7b6]49#include <arch/machine_func.h>
[973be64e]50
[7c3fb9b]51/*
52 * Size of the code jumping to the exception handler code
[96e0748d]53 * - J+NOP
[ffc277e]54 */
[96e0748d]55#define EXCEPTION_JUMP_SIZE 8
[ffc277e]56
[96e0748d]57#define TLB_EXC ((char *) 0x80000000)
58#define NORM_EXC ((char *) 0x80000180)
59#define CACHE_EXC ((char *) 0x80000100)
[ffc277e]60
[36df4109]61static void mips32_pre_mm_init(void);
62static void mips32_post_mm_init(void);
63static void mips32_post_smp_init(void);
64
65arch_ops_t mips32_ops = {
66 .pre_mm_init = mips32_pre_mm_init,
67 .post_mm_init = mips32_post_mm_init,
68 .post_smp_init = mips32_post_smp_init,
69};
70
71arch_ops_t *arch_ops = &mips32_ops;
[8449000]72
73/* Stack pointer saved when entering user mode */
[d86393c8]74// FIXME: This won't work with SMP unless thread creation is globally serialized.
75uintptr_t supervisor_sp;
[971cf31f]76
[98000fb]77size_t cpu_count = 0;
[96e0748d]78
[bcad855]79#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
80size_t sdram_size = 0;
81#endif
82
[06f96234]83/** Performs mips32-specific initialization before main_bsp() is called. */
[36df4109]84void mips32_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
[12c7f27]85{
[63a045c]86 init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
[a35b458]87
[98000fb]88 size_t i;
[4872160]89 for (i = 0; i < init.cnt; i++) {
[63a045c]90 init.tasks[i].paddr = KA2PA(bootinfo->taskmap.tasks[i].addr);
91 init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
[f4b1535]92 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
[63a045c]93 bootinfo->taskmap.tasks[i].name);
[96e0748d]94 }
[a35b458]95
[96e0748d]96 for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
97 if ((bootinfo->cpumap & (1 << i)) != 0)
98 cpu_count++;
[971cf31f]99 }
[bcad855]100
101#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
102 sdram_size = bootinfo->sdram_size;
103#endif
[260f678]104
[dabaa83]105 str_cpy(bargs, CONFIG_BOOT_ARGUMENTS_BUFLEN, bootinfo->bootargs);
106
[260f678]107 /* Initialize machine_ops pointer. */
108 machine_ops_init();
[12c7f27]109}
110
[36df4109]111void mips32_pre_mm_init(void)
[f761f1eb]112{
[24241cf]113 /* It is not assumed by default */
[22f7769]114 interrupts_disable();
[a35b458]115
[973be64e]116 /* Initialize dispatch table */
[7a8c866a]117 exception_init();
[3156582]118
[ffc277e]119 /* Copy the exception vectors to the right places */
[7688b5d]120 memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
[0abc2ae]121 smc_coherence(TLB_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]122 memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
[0abc2ae]123 smc_coherence(NORM_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]124 memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
[0abc2ae]125 smc_coherence(CACHE_EXC, EXCEPTION_JUMP_SIZE);
[a35b458]126
[f761f1eb]127 /*
[c7511ec]128 * Switch to BEV normal level so that exception vectors point to the
129 * kernel. Clear the error level.
[f761f1eb]130 */
[c7511ec]131 cp0_status_write(cp0_status_read() &
132 ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
[a35b458]133
[6da1013f]134 /*
135 * Mask all interrupts
[24241cf]136 */
137 cp0_mask_all_int();
[a35b458]138
[5bb8e45]139 debugger_init();
[f761f1eb]140}
[7eade45]141
[36df4109]142void mips32_post_mm_init(void)
[7eade45]143{
[7688b5d]144 interrupt_init();
[260f678]145
146 machine_init();
147 machine_output_init();
[7eade45]148}
[babcb148]149
[36df4109]150void mips32_post_smp_init(void)
[babcb148]151{
[eff1f033]152 /* Set platform name. */
[ae7ba7b6]153 sysinfo_set_item_data("platform", NULL,
154 (void *) machine_get_platform_name(),
155 str_size(machine_get_platform_name()));
[eff1f033]156
[260f678]157 machine_input_init();
[babcb148]158}
[2bd4fdf]159
[7f341820]160void calibrate_delay_loop(void)
161{
162}
163
[0f250f9]164void userspace(uspace_arg_t *kernel_uarg)
[2bd4fdf]165{
[b5ed4f8]166 /* EXL = 1, UM = 1, IE = 1 */
[2bd4fdf]167 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
[c7511ec]168 cp0_status_um_bit | cp0_status_ie_enabled_bit));
[7f1c620]169 cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
[2902e1bb]170 userspace_asm(((uintptr_t) kernel_uarg->uspace_stack +
171 kernel_uarg->uspace_stack_size),
[c7511ec]172 (uintptr_t) kernel_uarg->uspace_uarg,
173 (uintptr_t) kernel_uarg->uspace_entry);
[a35b458]174
[76d0981d]175 while (true)
[1433ecda]176 ;
[2bd4fdf]177}
178
[39cea6a]179/** Perform mips32 specific tasks needed before the new task is run. */
180void before_task_runs_arch(void)
181{
182}
183
184/** Perform mips32 specific tasks needed before the new thread is scheduled. */
[2bd4fdf]185void before_thread_runs_arch(void)
186{
[26aafe8]187 supervisor_sp =
[2277e03]188 (uintptr_t) &THREAD->kstack[STACK_SIZE];
[2bd4fdf]189}
[97f1691]190
191void after_thread_ran_arch(void)
192{
193}
[281b607]194
[f74bbaf]195void arch_reboot(void)
196{
[edebc15c]197 ___halt();
[76d0981d]198 while (true)
[1433ecda]199 ;
[6da1013f]200}
201
202/** Construct function pointer
203 *
204 * @param fptr function pointer structure
205 * @param addr function address
206 * @param caller calling function address
207 *
208 * @return address of the function pointer
209 *
210 */
211void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
212{
213 return addr;
[f74bbaf]214}
215
[3a2f8aa]216void irq_initialize_arch(irq_t *irq)
217{
218 (void) irq;
219}
220
[d227101]221/** @}
[b45c443]222 */
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