source: mainline/kernel/arch/mips32/src/exception.c@ f5dd4a1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f5dd4a1 was 68d8736, checked in by Jakub Jermar <jakub@…>, 6 years ago

Add kconsole input/output support to mips32/malta
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_mips32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/exception.h>
36#include <arch/interrupt.h>
37#include <arch/mm/tlb.h>
38#include <panic.h>
39#include <arch/cp0.h>
40#include <arch.h>
41#include <assert.h>
42#include <proc/thread.h>
43#include <interrupt.h>
44#include <halt.h>
45#include <ddi/irq.h>
46#include <arch/debugger.h>
47#include <symtab.h>
48#include <log.h>
49
50static const char *exctable[] = {
51 "Interrupt",
52 "TLB Modified",
53 "TLB Invalid",
54 "TLB Invalid Store",
55 "Address Error - load/instr. fetch",
56 "Address Error - store",
57 "Bus Error - fetch instruction",
58 "Bus Error - data reference",
59 "Syscall",
60 "BreakPoint",
61 "Reserved Instruction",
62 "Coprocessor Unusable",
63 "Arithmetic Overflow",
64 "Trap",
65 "Virtual Coherency - instruction",
66 "Floating Point",
67 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
68 "WatchHi/WatchLo", /* 23 */
69 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
70 "Virtual Coherency - data",
71};
72
73void istate_decode(istate_t *istate)
74{
75 log_printf("epc=%#010" PRIx32 "\tsta=%#010" PRIx32 "\t"
76 "lo =%#010" PRIx32 "\thi =%#010" PRIx32 "\n",
77 istate->epc, istate->status, istate->lo, istate->hi);
78
79 log_printf("a0 =%#010" PRIx32 "\ta1 =%#010" PRIx32 "\t"
80 "a2 =%#010" PRIx32 "\ta3 =%#010" PRIx32 "\n",
81 istate->a0, istate->a1, istate->a2, istate->a3);
82
83 log_printf("t0 =%#010" PRIx32 "\tt1 =%#010" PRIx32 "\t"
84 "t2 =%#010" PRIx32 "\tt3 =%#010" PRIx32 "\n",
85 istate->t0, istate->t1, istate->t2, istate->t3);
86
87 log_printf("t4 =%#010" PRIx32 "\tt5 =%#010" PRIx32 "\t"
88 "t6 =%#010" PRIx32 "\tt7 =%#010" PRIx32 "\n",
89 istate->t4, istate->t5, istate->t6, istate->t7);
90
91 log_printf("t8 =%#010" PRIx32 "\tt9 =%#010" PRIx32 "\t"
92 "v0 =%#010" PRIx32 "\tv1 =%#010" PRIx32 "\n",
93 istate->t8, istate->t9, istate->v0, istate->v1);
94
95 log_printf("s0 =%#010" PRIx32 "\ts1 =%#010" PRIx32 "\t"
96 "s2 =%#010" PRIx32 "\ts3 =%#010" PRIx32 "\n",
97 istate->s0, istate->s1, istate->s2, istate->s3);
98
99 log_printf("s4 =%#010" PRIx32 "\ts5 =%#010" PRIx32 "\t"
100 "s6 =%#010" PRIx32 "\ts7 =%#010" PRIx32 "\n",
101 istate->s4, istate->s5, istate->s6, istate->s7);
102
103 log_printf("s8 =%#010" PRIx32 "\tat =%#010" PRIx32 "\t"
104 "kt0=%#010" PRIx32 "\tkt1=%#010" PRIx32 "\n",
105 istate->s8, istate->at, istate->kt0, istate->kt1);
106
107 log_printf("sp =%#010" PRIx32 "\tra =%#010" PRIx32 "\t"
108 "gp =%#010" PRIx32 "\n",
109 istate->sp, istate->ra, istate->gp);
110}
111
112static void unhandled_exception(unsigned int n, istate_t *istate)
113{
114 fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]);
115 panic_badtrap(istate, n, "Unhandled exception %s.", exctable[n]);
116}
117
118static void reserved_instr_exception(unsigned int n, istate_t *istate)
119{
120 if (*((uint32_t *) istate->epc) == 0x7c03e83b) {
121 assert(THREAD);
122 istate->epc += 4;
123 istate->v1 = istate->kt1;
124 } else
125 unhandled_exception(n, istate);
126}
127
128static void breakpoint_exception(unsigned int n, istate_t *istate)
129{
130#ifdef CONFIG_DEBUG
131 debugger_bpoint(istate);
132#else
133 /*
134 * It is necessary to not re-execute BREAK instruction after
135 * returning from Exception handler
136 * (see page 138 in R4000 Manual for more information)
137 */
138 istate->epc += 4;
139#endif
140}
141
142static void tlbmod_exception(unsigned int n, istate_t *istate)
143{
144 tlb_modified(istate);
145}
146
147static void tlbinv_exception(unsigned int n, istate_t *istate)
148{
149 tlb_invalid(istate);
150}
151
152#ifdef CONFIG_FPU_LAZY
153static void cpuns_exception(unsigned int n, istate_t *istate)
154{
155 if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
156 scheduler_fpu_lazy_request();
157 else {
158 fault_if_from_uspace(istate,
159 "Unhandled Coprocessor Unusable Exception.");
160 panic_badtrap(istate, n,
161 "Unhandled Coprocessor Unusable Exception.");
162 }
163}
164#endif
165
166static void interrupt_exception(unsigned int n, istate_t *istate)
167{
168 uint32_t ip;
169 uint32_t im;
170
171 /* Decode interrupt number and process the interrupt */
172 ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
173 im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
174
175 unsigned int i;
176 for (i = 0; i < 8; i++) {
177
178 /*
179 * The interrupt could only occur if it is unmasked in the
180 * status register. On the other hand, an interrupt can be
181 * apparently pending even if it is masked, so we need to
182 * check both the masked and pending interrupts.
183 */
184 if (im & ip & (1 << i)) {
185 irq_t *irq = irq_dispatch_and_lock(i);
186 if (irq) {
187 /*
188 * The IRQ handler was found.
189 */
190 irq->handler(irq);
191 if (irq->cir)
192 irq->cir(irq->cir_arg, i);
193 irq_spinlock_unlock(&irq->lock, false);
194 } else {
195 /*
196 * Spurious interrupt.
197 */
198#ifdef CONFIG_DEBUG
199 log(LF_ARCH, LVL_DEBUG,
200 "cpu%u: spurious interrupt (inum=%u)",
201 CPU->id, i);
202#endif
203 }
204 }
205 }
206}
207
208/** Handle syscall userspace call */
209static void syscall_exception(unsigned int n, istate_t *istate)
210{
211 fault_if_from_uspace(istate, "Syscall is handled through shortcut.");
212}
213
214void exception_init(void)
215{
216 unsigned int i;
217
218 /* Clear exception table */
219 for (i = 0; i < IVT_ITEMS; i++)
220 exc_register(i, "undef", false,
221 (iroutine_t) unhandled_exception);
222
223 exc_register(EXC_Bp, "bkpoint", true,
224 (iroutine_t) breakpoint_exception);
225 exc_register(EXC_RI, "resinstr", true,
226 (iroutine_t) reserved_instr_exception);
227 exc_register(EXC_Mod, "tlb_mod", true,
228 (iroutine_t) tlbmod_exception);
229 exc_register(EXC_TLBL, "tlbinvl", true,
230 (iroutine_t) tlbinv_exception);
231 exc_register(EXC_TLBS, "tlbinvl", true,
232 (iroutine_t) tlbinv_exception);
233 exc_register(EXC_Int, "interrupt", true,
234 (iroutine_t) interrupt_exception);
235
236#ifdef CONFIG_FPU_LAZY
237 exc_register(EXC_CpU, "cpunus", true,
238 (iroutine_t) cpuns_exception);
239#endif
240
241 exc_register(EXC_Sys, "syscall", true,
242 (iroutine_t) syscall_exception);
243}
244
245/** @}
246 */
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