[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Ondrej Palkovsky
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[2f40fe4] | 29 | /** @addtogroup mips32
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[06e1e95] | 35 | #ifndef KERN_mips32_ATOMIC_H_
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| 36 | #define KERN_mips32_ATOMIC_H_
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[f761f1eb] | 37 |
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[7f341820] | 38 | #define atomic_inc(x) ((void) atomic_add(x, 1))
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| 39 | #define atomic_dec(x) ((void) atomic_add(x, -1))
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[e3f41b6] | 40 |
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[7f341820] | 41 | #define atomic_postinc(x) (atomic_add(x, 1) - 1)
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| 42 | #define atomic_postdec(x) (atomic_add(x, -1) + 1)
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[73a4bab] | 43 |
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[7f341820] | 44 | #define atomic_preinc(x) atomic_add(x, 1)
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| 45 | #define atomic_predec(x) atomic_add(x, -1)
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[73a4bab] | 46 |
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[e507afa] | 47 | /* Atomic addition of immediate value.
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[e3f41b6] | 48 | *
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[e507afa] | 49 | * @param val Memory location to which will be the immediate value added.
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| 50 | * @param i Signed immediate that will be added to *val.
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[e3f41b6] | 51 | *
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[e507afa] | 52 | * @return Value after addition.
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[e3f41b6] | 53 | */
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[23684b7] | 54 | static inline long atomic_add(atomic_t *val, int i)
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[e3f41b6] | 55 | {
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[23684b7] | 56 | long tmp, v;
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[7f341820] | 57 |
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[e7b7be3f] | 58 | asm volatile (
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[e3f41b6] | 59 | "1:\n"
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[e507afa] | 60 | " ll %0, %1\n"
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[7f341820] | 61 | " addu %0, %0, %3\n" /* same as addi, but never traps on overflow */
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| 62 | " move %2, %0\n"
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[e507afa] | 63 | " sc %0, %1\n"
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[7f341820] | 64 | " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
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[2f40fe4] | 65 | " nop\n"
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[5336643] | 66 | : "=&r" (tmp), "+m" (val->count), "=&r" (v)
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[2a3124c] | 67 | : "r" (i), "i" (0)
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[7f341820] | 68 | );
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| 69 |
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| 70 | return v;
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| 71 | }
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[e507afa] | 72 |
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[7f341820] | 73 | static inline uint32_t test_and_set(atomic_t *val) {
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| 74 | uint32_t tmp, v;
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| 75 |
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| 76 | asm volatile (
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| 77 | "1:\n"
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| 78 | " ll %2, %1\n"
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| 79 | " bnez %2, 2f\n"
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| 80 | " li %0, %3\n"
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| 81 | " sc %0, %1\n"
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| 82 | " beqz %0, 1b\n"
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| 83 | "2:\n"
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| 84 | : "=&r" (tmp), "+m" (val->count), "=&r" (v)
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| 85 | : "i" (1)
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| 86 | );
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| 87 |
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[e507afa] | 88 | return v;
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[e3f41b6] | 89 | }
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| 90 |
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[88d653c] | 91 | static inline void atomic_lock_arch(atomic_t *val) {
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| 92 | do {
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| 93 | while (val->count)
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| 94 | ;
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| 95 | } while (test_and_set(val));
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| 96 | }
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| 97 |
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[f761f1eb] | 98 | #endif
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[b45c443] | 99 |
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[2f40fe4] | 100 | /** @}
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[b45c443] | 101 | */
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