source: mainline/kernel/arch/mips32/include/atomic.h@ 88d653c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 88d653c was 88d653c, checked in by Jakub Jermar <jakub@…>, 16 years ago

Add simple atomic_lock_arch() to mips32 so that it builds for the msim target.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 * Copyright (c) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_mips32_ATOMIC_H_
36#define KERN_mips32_ATOMIC_H_
37
38#define atomic_inc(x) ((void) atomic_add(x, 1))
39#define atomic_dec(x) ((void) atomic_add(x, -1))
40
41#define atomic_postinc(x) (atomic_add(x, 1) - 1)
42#define atomic_postdec(x) (atomic_add(x, -1) + 1)
43
44#define atomic_preinc(x) atomic_add(x, 1)
45#define atomic_predec(x) atomic_add(x, -1)
46
47/* Atomic addition of immediate value.
48 *
49 * @param val Memory location to which will be the immediate value added.
50 * @param i Signed immediate that will be added to *val.
51 *
52 * @return Value after addition.
53 */
54static inline long atomic_add(atomic_t *val, int i)
55{
56 long tmp, v;
57
58 asm volatile (
59 "1:\n"
60 " ll %0, %1\n"
61 " addu %0, %0, %3\n" /* same as addi, but never traps on overflow */
62 " move %2, %0\n"
63 " sc %0, %1\n"
64 " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
65 " nop\n"
66 : "=&r" (tmp), "+m" (val->count), "=&r" (v)
67 : "r" (i), "i" (0)
68 );
69
70 return v;
71}
72
73static inline uint32_t test_and_set(atomic_t *val) {
74 uint32_t tmp, v;
75
76 asm volatile (
77 "1:\n"
78 " ll %2, %1\n"
79 " bnez %2, 2f\n"
80 " li %0, %3\n"
81 " sc %0, %1\n"
82 " beqz %0, 1b\n"
83 "2:\n"
84 : "=&r" (tmp), "+m" (val->count), "=&r" (v)
85 : "i" (1)
86 );
87
88 return v;
89}
90
91static inline void atomic_lock_arch(atomic_t *val) {
92 do {
93 while (val->count)
94 ;
95 } while (test_and_set(val));
96}
97
98#endif
99
100/** @}
101 */
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