source: mainline/kernel/arch/ia64/src/start.S@ 3193c05

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3193c05 was fae1647, checked in by Jakub Jermar <jakub@…>, 15 years ago

Use IP-relative instead of indirect branch to main_bsp().

  • Property mode set to 100644
File size: 4.5 KB
RevLine 
[30ef8ce]1#
[df4ed85]2# Copyright (c) 2005 Jakub Jermar
[30ef8ce]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[802bb95]29#include <arch/register.h>
[5ac2e61]30#include <arch/mm/page.h>
31#include <arch/mm/asid.h>
32#include <mm/asid.h>
33
[5bda2f3e]34#define RR_MASK (0xFFFFFFFF00000002)
35#define RID_SHIFT 8
36#define PS_SHIFT 2
[7208b6c]37
[5bda2f3e]38#define KERNEL_TRANSLATION_I 0x0010000000000661
39#define KERNEL_TRANSLATION_D 0x0010000000000661
40#define KERNEL_TRANSLATION_VIO 0x0010000000000671
41#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
42#define KERNEL_TRANSLATION_FW 0x00100000F0000671
[5ac2e61]43
[9faddb3]44.section K_TEXT_START, "ax"
[00a44bc]45
[30ef8ce]46.global kernel_image_start
47
[2217ac3]48stack0:
[30ef8ce]49kernel_image_start:
[7f1bfce]50 .auto
[5bda2f3e]51
[7208b6c]52 mov psr.l = r0
53 srlz.i
54 srlz.d
[5bda2f3e]55
[481c520]56 # Fill TR.i and TR.d using Region Register #VRN_KERNEL
[5bda2f3e]57
[15819e37]58 movl r8 = (VRN_KERNEL << VRN_SHIFT)
59 mov r9 = rr[r8]
[5bda2f3e]60
[15819e37]61 movl r10 = (RR_MASK)
62 and r9 = r10, r9
[d9ee2ea]63 movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
[5bda2f3e]64 or r9 = r10, r9
65
[15819e37]66 mov rr[r8] = r9
[5bda2f3e]67
[15819e37]68 movl r8 = (VRN_KERNEL << VRN_SHIFT)
69 mov cr.ifa = r8
[5bda2f3e]70
[acee917]71 mov r11 = cr.itir
72 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
73 or r10 = r10, r11
74 mov cr.itir = r10
[5bda2f3e]75
[15819e37]76 movl r10 = (KERNEL_TRANSLATION_I)
77 itr.i itr[r0] = r10
78 movl r10 = (KERNEL_TRANSLATION_D)
79 itr.d dtr[r0] = r10
[5bda2f3e]80
[7208b6c]81 movl r7 = 1
82 movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
83 mov cr.ifa = r8
84 movl r10 = (KERNEL_TRANSLATION_VIO)
85 itr.d dtr[r7] = r10
[5bda2f3e]86
[acee917]87 mov r11 = cr.itir
88 movl r10 = ~0xfc
89 and r10 = r10, r11
90 movl r11 = (IO_PAGE_WIDTH << PS_SHIFT)
91 or r10 = r10, r11
92 mov cr.itir = r10
[5bda2f3e]93
[7208b6c]94 movl r7 = 2
95 movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
96 mov cr.ifa = r8
97 movl r10 = (KERNEL_TRANSLATION_IO)
98 itr.d dtr[r7] = r10
[5bda2f3e]99
100 # Setup mapping for firmware area (also SAPIC)
101
[acee917]102 mov r11 = cr.itir
103 movl r10 = ~0xfc
104 and r10 = r10, r11
105 movl r11 = (FW_PAGE_WIDTH << PS_SHIFT)
106 or r10 = r10, r11
107 mov cr.itir = r10
[5bda2f3e]108
[59e4864]109 movl r7 = 3
110 movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
111 mov cr.ifa = r8
112 movl r10 = (KERNEL_TRANSLATION_FW)
113 itr.d dtr[r7] = r10
[5bda2f3e]114
[93d66ef]115 # Initialize DSR
116
117 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
118 mov r9 = cr.dcr
119 or r10 = r10, r9
120 mov cr.dcr = r10
121
[666773c]122 # Initialize PSR
[5bda2f3e]123
[15819e37]124 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
125 mov r9 = psr
[5bda2f3e]126
[15819e37]127 or r10 = r10, r9
128 mov cr.ipsr = r10
129 mov cr.ifs = r0
130 movl r8 = paging_start
131 mov cr.iip = r8
[802bb95]132 srlz.d
[5ac2e61]133 srlz.i
[5bda2f3e]134
[481c520]135 .explicit
[5bda2f3e]136
[481c520]137 /*
[0e56eb1a]138 * Return From Interrupt is the only way to
139 * fill the upper half word of PSR.
[481c520]140 */
[acee917]141 rfi ;;
[085434a]142
143.global paging_start
144paging_start:
[5bda2f3e]145
[481c520]146 /*
147 * Now we are paging.
148 */
[5bda2f3e]149
[666773c]150 # Switch to register bank 1
[802bb95]151 bsw.1
[5bda2f3e]152
[666773c]153 # Initialize register stack
[7f1bfce]154 mov ar.rsc = r0
[15819e37]155 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
[5ac2e61]156 mov ar.bspstore = r8
[7f1bfce]157 loadrs
[5bda2f3e]158
[666773c]159 # Initialize memory stack to some sane value
[15819e37]160 movl r12 = stack0 ;;
[5bda2f3e]161 add r12 = -16, r12 /* allocate a scratch area on the stack */
162
[666773c]163 # Initialize gp (Global Pointer) register
[5bda2f3e]164 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
165 or r20 = r20, r1 ;;
[19b5929]166 movl r1 = kernel_image_start
[7a9364c]167
[481c520]168 /*
[19b5929]169 * Initialize bootinfo on BSP.
[481c520]170 */
[e5c1186]171 addl r21 = @gprel(bootinfo), gp ;;
172 st8 [r21] = r20
[5bda2f3e]173
[15819e37]174 ssm (1 << 19) ;; /* Disable f32 - f127 */
175 srlz.i
176 srlz.d ;;
[5bda2f3e]177
[6ecc8bce]178 br.call.sptk.many b0 = arch_pre_main
[fae1647]1790:
180 br.call.sptk.many b0 = main_bsp
[2a0047fc]1810:
[47d78c6]182 br 0b
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