source: mainline/kernel/arch/ia64/src/start.S@ 3193c05

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3193c05 was fae1647, checked in by Jakub Jermar <jakub@…>, 15 years ago

Use IP-relative instead of indirect branch to main_bsp().

  • Property mode set to 100644
File size: 4.5 KB
Line 
1#
2# Copyright (c) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/register.h>
30#include <arch/mm/page.h>
31#include <arch/mm/asid.h>
32#include <mm/asid.h>
33
34#define RR_MASK (0xFFFFFFFF00000002)
35#define RID_SHIFT 8
36#define PS_SHIFT 2
37
38#define KERNEL_TRANSLATION_I 0x0010000000000661
39#define KERNEL_TRANSLATION_D 0x0010000000000661
40#define KERNEL_TRANSLATION_VIO 0x0010000000000671
41#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
42#define KERNEL_TRANSLATION_FW 0x00100000F0000671
43
44.section K_TEXT_START, "ax"
45
46.global kernel_image_start
47
48stack0:
49kernel_image_start:
50 .auto
51
52 mov psr.l = r0
53 srlz.i
54 srlz.d
55
56 # Fill TR.i and TR.d using Region Register #VRN_KERNEL
57
58 movl r8 = (VRN_KERNEL << VRN_SHIFT)
59 mov r9 = rr[r8]
60
61 movl r10 = (RR_MASK)
62 and r9 = r10, r9
63 movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
64 or r9 = r10, r9
65
66 mov rr[r8] = r9
67
68 movl r8 = (VRN_KERNEL << VRN_SHIFT)
69 mov cr.ifa = r8
70
71 mov r11 = cr.itir
72 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
73 or r10 = r10, r11
74 mov cr.itir = r10
75
76 movl r10 = (KERNEL_TRANSLATION_I)
77 itr.i itr[r0] = r10
78 movl r10 = (KERNEL_TRANSLATION_D)
79 itr.d dtr[r0] = r10
80
81 movl r7 = 1
82 movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
83 mov cr.ifa = r8
84 movl r10 = (KERNEL_TRANSLATION_VIO)
85 itr.d dtr[r7] = r10
86
87 mov r11 = cr.itir
88 movl r10 = ~0xfc
89 and r10 = r10, r11
90 movl r11 = (IO_PAGE_WIDTH << PS_SHIFT)
91 or r10 = r10, r11
92 mov cr.itir = r10
93
94 movl r7 = 2
95 movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
96 mov cr.ifa = r8
97 movl r10 = (KERNEL_TRANSLATION_IO)
98 itr.d dtr[r7] = r10
99
100 # Setup mapping for firmware area (also SAPIC)
101
102 mov r11 = cr.itir
103 movl r10 = ~0xfc
104 and r10 = r10, r11
105 movl r11 = (FW_PAGE_WIDTH << PS_SHIFT)
106 or r10 = r10, r11
107 mov cr.itir = r10
108
109 movl r7 = 3
110 movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
111 mov cr.ifa = r8
112 movl r10 = (KERNEL_TRANSLATION_FW)
113 itr.d dtr[r7] = r10
114
115 # Initialize DSR
116
117 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
118 mov r9 = cr.dcr
119 or r10 = r10, r9
120 mov cr.dcr = r10
121
122 # Initialize PSR
123
124 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
125 mov r9 = psr
126
127 or r10 = r10, r9
128 mov cr.ipsr = r10
129 mov cr.ifs = r0
130 movl r8 = paging_start
131 mov cr.iip = r8
132 srlz.d
133 srlz.i
134
135 .explicit
136
137 /*
138 * Return From Interrupt is the only way to
139 * fill the upper half word of PSR.
140 */
141 rfi ;;
142
143.global paging_start
144paging_start:
145
146 /*
147 * Now we are paging.
148 */
149
150 # Switch to register bank 1
151 bsw.1
152
153 # Initialize register stack
154 mov ar.rsc = r0
155 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
156 mov ar.bspstore = r8
157 loadrs
158
159 # Initialize memory stack to some sane value
160 movl r12 = stack0 ;;
161 add r12 = -16, r12 /* allocate a scratch area on the stack */
162
163 # Initialize gp (Global Pointer) register
164 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
165 or r20 = r20, r1 ;;
166 movl r1 = kernel_image_start
167
168 /*
169 * Initialize bootinfo on BSP.
170 */
171 addl r21 = @gprel(bootinfo), gp ;;
172 st8 [r21] = r20
173
174 ssm (1 << 19) ;; /* Disable f32 - f127 */
175 srlz.i
176 srlz.d ;;
177
178 br.call.sptk.many b0 = arch_pre_main
1790:
180 br.call.sptk.many b0 = main_bsp
1810:
182 br 0b
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