[6d7ffa65] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Jakub Jermar
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| 3 | * Copyright (c) 2006 Jakub Vana
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[6d7ffa65] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[9979acb] | 30 | /** @addtogroup ia64mm
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[b45c443] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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[6d7ffa65] | 36 | #include <arch/mm/page.h>
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| 37 | #include <genarch/mm/page_ht.h>
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[c2b95d3] | 38 | #include <mm/asid.h>
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[457d18a] | 39 | #include <arch/mm/asid.h>
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[68091bd] | 40 | #include <arch/mm/vhpt.h>
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[c2b95d3] | 41 | #include <arch/types.h>
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[6461d67c] | 42 | #include <print.h>
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[6d7ffa65] | 43 | #include <mm/page.h>
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[c2b95d3] | 44 | #include <mm/frame.h>
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[6d7ffa65] | 45 | #include <config.h>
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| 46 | #include <panic.h>
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[2a003d5b] | 47 | #include <arch/asm.h>
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[c2b95d3] | 48 | #include <arch/barrier.h>
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[849386a] | 49 | #include <memstr.h>
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[59e4864] | 50 | #include <align.h>
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[9979acb] | 51 | #include <ddi/ddi.h>
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| 52 |
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| 53 | /** Physical memory area for devices. */
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| 54 | static parea_t dev_area;
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[6d7ffa65] | 55 |
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[c7ec94a4] | 56 | static void set_environment(void);
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[457d18a] | 57 |
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| 58 | /** Initialize ia64 virtual address translation subsystem. */
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| 59 | void page_arch_init(void)
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| 60 | {
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[f5935ed] | 61 | page_mapping_operations = &ht_mapping_operations;
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[457d18a] | 62 | pk_disable();
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[c7ec94a4] | 63 | set_environment();
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[457d18a] | 64 | }
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| 65 |
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[c2b95d3] | 66 | /** Initialize VHPT and region registers. */
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[c7ec94a4] | 67 | void set_environment(void)
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[fd537a0] | 68 | {
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[c2b95d3] | 69 | region_register rr;
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| 70 | pta_register pta;
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[fd537a0] | 71 | int i;
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[68091bd] | 72 | #ifdef CONFIG_VHPT
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[7f1c620] | 73 | uintptr_t vhpt_base;
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[68091bd] | 74 | #endif
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[5ac2e61] | 75 |
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[c2b95d3] | 76 | /*
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| 77 | * First set up kernel region register.
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[a0d74fd] | 78 | * This is redundant (see start.S) but we keep it here just for sure.
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[c2b95d3] | 79 | */
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| 80 | rr.word = rr_read(VRN_KERNEL);
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| 81 | rr.map.ve = 0; /* disable VHPT walker */
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| 82 | rr.map.ps = PAGE_WIDTH;
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[a0d74fd] | 83 | rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
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[c2b95d3] | 84 | rr_write(VRN_KERNEL, rr.word);
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| 85 | srlz_i();
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| 86 | srlz_d();
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[a0d74fd] | 87 |
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[c2b95d3] | 88 | /*
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[9ad03fe] | 89 | * And setup the rest of region register.
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[c2b95d3] | 90 | */
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| 91 | for(i = 0; i < REGION_REGISTERS; i++) {
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| 92 | /* skip kernel rr */
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| 93 | if (i == VRN_KERNEL)
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| 94 | continue;
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[6461d67c] | 95 |
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[9459255] | 96 | rr.word = rr_read(i);
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[849386a] | 97 | rr.map.ve = 0; /* disable VHPT walker */
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[9ad03fe] | 98 | rr.map.rid = RID_KERNEL;
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| 99 | rr.map.ps = PAGE_WIDTH;
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[c2b95d3] | 100 | rr_write(i, rr.word);
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| 101 | srlz_i();
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| 102 | srlz_d();
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| 103 | }
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[6461d67c] | 104 |
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[68091bd] | 105 | #ifdef CONFIG_VHPT
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| 106 | vhpt_base = vhpt_set_up();
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| 107 | #endif
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[c2b95d3] | 108 | /*
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| 109 | * Set up PTA register.
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| 110 | */
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| 111 | pta.word = pta_read();
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[68091bd] | 112 | #ifndef CONFIG_VHPT
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[c2b95d3] | 113 | pta.map.ve = 0; /* disable VHPT walker */
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[68091bd] | 114 | pta.map.base = 0 >> PTA_BASE_SHIFT;
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| 115 | #else
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| 116 | pta.map.ve = 1; /* enable VHPT walker */
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| 117 | pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
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| 118 | #endif
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[c2b95d3] | 119 | pta.map.vf = 1; /* large entry format */
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| 120 | pta.map.size = VHPT_WIDTH;
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| 121 | pta_write(pta.word);
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| 122 | srlz_i();
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| 123 | srlz_d();
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| 124 | }
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[fd537a0] | 125 |
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[849386a] | 126 | /** Calculate address of collision chain from VPN and ASID.
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| 127 | *
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[457d18a] | 128 | * Interrupts must be disabled.
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[849386a] | 129 | *
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[666773c] | 130 | * @param page Address of virtual page including VRN bits.
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| 131 | * @param asid Address space identifier.
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[849386a] | 132 | *
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[666773c] | 133 | * @return VHPT entry address.
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[849386a] | 134 | */
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[7f1c620] | 135 | vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
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[849386a] | 136 | {
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| 137 | region_register rr_save, rr;
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[457d18a] | 138 | index_t vrn;
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| 139 | rid_t rid;
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[c7ec94a4] | 140 | vhpt_entry_t *v;
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[849386a] | 141 |
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[457d18a] | 142 | vrn = page >> VRN_SHIFT;
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| 143 | rid = ASID2RID(asid, vrn);
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| 144 |
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| 145 | rr_save.word = rr_read(vrn);
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| 146 | if (rr_save.map.rid == rid) {
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| 147 | /*
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| 148 | * The RID is already in place, compute thash and return.
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| 149 | */
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[c7ec94a4] | 150 | v = (vhpt_entry_t *) thash(page);
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| 151 | return v;
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[457d18a] | 152 | }
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| 153 |
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| 154 | /*
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| 155 | * The RID must be written to some region register.
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| 156 | * To speed things up, register indexed by vrn is used.
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| 157 | */
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[849386a] | 158 | rr.word = rr_save.word;
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[457d18a] | 159 | rr.map.rid = rid;
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| 160 | rr_write(vrn, rr.word);
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[849386a] | 161 | srlz_i();
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[c7ec94a4] | 162 | v = (vhpt_entry_t *) thash(page);
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[457d18a] | 163 | rr_write(vrn, rr_save.word);
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[849386a] | 164 | srlz_i();
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| 165 | srlz_d();
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| 166 |
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[c7ec94a4] | 167 | return v;
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[849386a] | 168 | }
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[457d18a] | 169 |
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| 170 | /** Compare ASID and VPN against PTE.
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| 171 | *
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| 172 | * Interrupts must be disabled.
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| 173 | *
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[666773c] | 174 | * @param page Address of virtual page including VRN bits.
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| 175 | * @param asid Address space identifier.
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[457d18a] | 176 | *
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[666773c] | 177 | * @return True if page and asid match the page and asid of t,
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| 178 | * false otherwise.
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[457d18a] | 179 | */
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[7f1c620] | 180 | bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
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[457d18a] | 181 | {
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| 182 | region_register rr_save, rr;
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| 183 | index_t vrn;
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| 184 | rid_t rid;
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| 185 | bool match;
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| 186 |
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[c7ec94a4] | 187 | ASSERT(v);
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[457d18a] | 188 |
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| 189 | vrn = page >> VRN_SHIFT;
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| 190 | rid = ASID2RID(asid, vrn);
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| 191 |
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| 192 | rr_save.word = rr_read(vrn);
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| 193 | if (rr_save.map.rid == rid) {
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| 194 | /*
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| 195 | * The RID is already in place, compare ttag with t and return.
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| 196 | */
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[c7ec94a4] | 197 | return ttag(page) == v->present.tag.tag_word;
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[457d18a] | 198 | }
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| 199 |
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| 200 | /*
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| 201 | * The RID must be written to some region register.
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| 202 | * To speed things up, register indexed by vrn is used.
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| 203 | */
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| 204 | rr.word = rr_save.word;
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| 205 | rr.map.rid = rid;
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| 206 | rr_write(vrn, rr.word);
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| 207 | srlz_i();
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[c7ec94a4] | 208 | match = (ttag(page) == v->present.tag.tag_word);
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[457d18a] | 209 | rr_write(vrn, rr_save.word);
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| 210 | srlz_i();
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| 211 | srlz_d();
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| 212 |
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| 213 | return match;
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| 214 | }
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| 215 |
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| 216 | /** Set up one VHPT entry.
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| 217 | *
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[abbc16e] | 218 | * @param v VHPT entry to be set up.
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[666773c] | 219 | * @param page Virtual address of the page mapped by the entry.
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| 220 | * @param asid Address space identifier of the address space to which
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| 221 | * page belongs.
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| 222 | * @param frame Physical address of the frame to wich page is mapped.
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| 223 | * @param flags Different flags for the mapping.
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[457d18a] | 224 | */
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[666773c] | 225 | void
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| 226 | vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame,
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| 227 | int flags)
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[457d18a] | 228 | {
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| 229 | region_register rr_save, rr;
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| 230 | index_t vrn;
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| 231 | rid_t rid;
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[7f1c620] | 232 | uint64_t tag;
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[457d18a] | 233 |
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[c7ec94a4] | 234 | ASSERT(v);
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[457d18a] | 235 |
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| 236 | vrn = page >> VRN_SHIFT;
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| 237 | rid = ASID2RID(asid, vrn);
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| 238 |
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| 239 | /*
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| 240 | * Compute ttag.
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| 241 | */
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| 242 | rr_save.word = rr_read(vrn);
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| 243 | rr.word = rr_save.word;
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| 244 | rr.map.rid = rid;
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| 245 | rr_write(vrn, rr.word);
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| 246 | srlz_i();
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| 247 | tag = ttag(page);
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| 248 | rr_write(vrn, rr_save.word);
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| 249 | srlz_i();
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| 250 | srlz_d();
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| 251 |
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| 252 | /*
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| 253 | * Clear the entry.
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| 254 | */
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[c7ec94a4] | 255 | v->word[0] = 0;
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| 256 | v->word[1] = 0;
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| 257 | v->word[2] = 0;
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| 258 | v->word[3] = 0;
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[457d18a] | 259 |
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[c7ec94a4] | 260 | v->present.p = true;
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[666773c] | 261 | v->present.ma = (flags & PAGE_CACHEABLE) ?
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| 262 | MA_WRITEBACK : MA_UNCACHEABLE;
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[c7ec94a4] | 263 | v->present.a = false; /* not accessed */
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| 264 | v->present.d = false; /* not dirty */
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| 265 | v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
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| 266 | v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
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| 267 | v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
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| 268 | v->present.ppn = frame >> PPN_SHIFT;
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| 269 | v->present.ed = false; /* exception not deffered */
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| 270 | v->present.ps = PAGE_WIDTH;
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| 271 | v->present.key = 0;
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| 272 | v->present.tag.tag_word = tag;
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[457d18a] | 273 | }
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[b45c443] | 274 |
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[38f6add] | 275 | uintptr_t hw_map(uintptr_t physaddr, size_t size __attribute__ ((unused)))
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[59e4864] | 276 | {
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[38f6add] | 277 | /* This is a dirty hack. */
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| 278 | return PA2KA(physaddr);
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[59e4864] | 279 | }
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| 280 |
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[9979acb] | 281 | void hw_area(void)
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[ae318d3] | 282 | {
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[9979acb] | 283 | dev_area.pbase = end_frame;
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| 284 | dev_area.frames = SIZE2FRAMES(0x7fffffffffffffffUL - end_frame);
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| 285 | ddi_parea_register(&dev_area);
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[ae318d3] | 286 | }
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| 287 |
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[06e1e95] | 288 | /** @}
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[b45c443] | 289 | */
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