source: mainline/kernel/arch/ia64/src/mm/page.c@ 05882233

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 05882233 was 05882233, checked in by Jiří Zárevúcky <jiri.zarevucky@…>, 7 years ago

Unify various barrier includes into <barrier.h>

  • Property mode set to 100644
File size: 6.3 KB
RevLine 
[6d7ffa65]1/*
[df4ed85]2 * Copyright (c) 2006 Jakub Jermar
3 * Copyright (c) 2006 Jakub Vana
[6d7ffa65]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
[9979acb]30/** @addtogroup ia64mm
[b45c443]31 * @{
32 */
33/** @file
34 */
35
[6d7ffa65]36#include <arch/mm/page.h>
[63e27ef]37#include <assert.h>
[6d7ffa65]38#include <genarch/mm/page_ht.h>
[c2b95d3]39#include <mm/asid.h>
[457d18a]40#include <arch/mm/asid.h>
[68091bd]41#include <arch/mm/vhpt.h>
[d99c1d2]42#include <typedefs.h>
[6461d67c]43#include <print.h>
[6d7ffa65]44#include <mm/page.h>
[c2b95d3]45#include <mm/frame.h>
[6d7ffa65]46#include <config.h>
47#include <panic.h>
[2a003d5b]48#include <arch/asm.h>
[05882233]49#include <barrier.h>
[59e4864]50#include <align.h>
[6d7ffa65]51
[c7ec94a4]52static void set_environment(void);
[457d18a]53
54/** Initialize ia64 virtual address translation subsystem. */
55void page_arch_init(void)
56{
[f5935ed]57 page_mapping_operations = &ht_mapping_operations;
[457d18a]58 pk_disable();
[c7ec94a4]59 set_environment();
[457d18a]60}
61
[c2b95d3]62/** Initialize VHPT and region registers. */
[c7ec94a4]63void set_environment(void)
[fd537a0]64{
[5bda2f3e]65 region_register_t rr;
66 pta_register_t pta;
[fd537a0]67 int i;
[e49e234]68#ifdef CONFIG_VHPT
[7f1c620]69 uintptr_t vhpt_base;
[68091bd]70#endif
[5ac2e61]71
[c2b95d3]72 /*
[d9ee2ea]73 * Set up kernel region registers.
74 * VRN_KERNEL has already been set in start.S.
75 * For paranoia reasons, we set it again.
[c2b95d3]76 */
[18b6a88]77 for (i = 0; i < REGION_REGISTERS; i++) {
[9459255]78 rr.word = rr_read(i);
[849386a]79 rr.map.ve = 0; /* disable VHPT walker */
[d9ee2ea]80 rr.map.rid = ASID2RID(ASID_KERNEL, i);
[9ad03fe]81 rr.map.ps = PAGE_WIDTH;
[c2b95d3]82 rr_write(i, rr.word);
83 srlz_i();
84 srlz_d();
85 }
[6461d67c]86
[1b20da0]87#ifdef CONFIG_VHPT
[68091bd]88 vhpt_base = vhpt_set_up();
89#endif
[c2b95d3]90 /*
91 * Set up PTA register.
92 */
93 pta.word = pta_read();
[68091bd]94#ifndef CONFIG_VHPT
[c2b95d3]95 pta.map.ve = 0; /* disable VHPT walker */
[68091bd]96 pta.map.base = 0 >> PTA_BASE_SHIFT;
97#else
98 pta.map.ve = 1; /* enable VHPT walker */
99 pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
100#endif
[c2b95d3]101 pta.map.vf = 1; /* large entry format */
102 pta.map.size = VHPT_WIDTH;
103 pta_write(pta.word);
104 srlz_i();
105 srlz_d();
106}
[fd537a0]107
[849386a]108/** Calculate address of collision chain from VPN and ASID.
109 *
[457d18a]110 * Interrupts must be disabled.
[849386a]111 *
[666773c]112 * @param page Address of virtual page including VRN bits.
113 * @param asid Address space identifier.
[849386a]114 *
[666773c]115 * @return VHPT entry address.
[849386a]116 */
[7f1c620]117vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
[849386a]118{
[5bda2f3e]119 region_register_t rr_save, rr;
[98000fb]120 size_t vrn;
[457d18a]121 rid_t rid;
[c7ec94a4]122 vhpt_entry_t *v;
[849386a]123
[457d18a]124 vrn = page >> VRN_SHIFT;
125 rid = ASID2RID(asid, vrn);
[a35b458]126
[457d18a]127 rr_save.word = rr_read(vrn);
128 if (rr_save.map.rid == rid) {
129 /*
130 * The RID is already in place, compute thash and return.
131 */
[c7ec94a4]132 v = (vhpt_entry_t *) thash(page);
133 return v;
[457d18a]134 }
[a35b458]135
[457d18a]136 /*
137 * The RID must be written to some region register.
138 * To speed things up, register indexed by vrn is used.
139 */
[849386a]140 rr.word = rr_save.word;
[457d18a]141 rr.map.rid = rid;
142 rr_write(vrn, rr.word);
[849386a]143 srlz_i();
[c7ec94a4]144 v = (vhpt_entry_t *) thash(page);
[457d18a]145 rr_write(vrn, rr_save.word);
[849386a]146 srlz_i();
147 srlz_d();
148
[c7ec94a4]149 return v;
[849386a]150}
[457d18a]151
152/** Compare ASID and VPN against PTE.
153 *
154 * Interrupts must be disabled.
155 *
[666773c]156 * @param page Address of virtual page including VRN bits.
157 * @param asid Address space identifier.
[457d18a]158 *
[666773c]159 * @return True if page and asid match the page and asid of t,
160 * false otherwise.
[457d18a]161 */
[7f1c620]162bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
[457d18a]163{
[5bda2f3e]164 region_register_t rr_save, rr;
[98000fb]165 size_t vrn;
[457d18a]166 rid_t rid;
167 bool match;
168
[63e27ef]169 assert(v);
[457d18a]170
171 vrn = page >> VRN_SHIFT;
172 rid = ASID2RID(asid, vrn);
[a35b458]173
[457d18a]174 rr_save.word = rr_read(vrn);
175 if (rr_save.map.rid == rid) {
176 /*
177 * The RID is already in place, compare ttag with t and return.
178 */
[c7ec94a4]179 return ttag(page) == v->present.tag.tag_word;
[457d18a]180 }
[a35b458]181
[457d18a]182 /*
183 * The RID must be written to some region register.
184 * To speed things up, register indexed by vrn is used.
185 */
186 rr.word = rr_save.word;
187 rr.map.rid = rid;
188 rr_write(vrn, rr.word);
189 srlz_i();
[c7ec94a4]190 match = (ttag(page) == v->present.tag.tag_word);
[457d18a]191 rr_write(vrn, rr_save.word);
192 srlz_i();
193 srlz_d();
194
[1b20da0]195 return match;
[457d18a]196}
197
198/** Set up one VHPT entry.
199 *
[abbc16e]200 * @param v VHPT entry to be set up.
[666773c]201 * @param page Virtual address of the page mapped by the entry.
202 * @param asid Address space identifier of the address space to which
203 * page belongs.
204 * @param frame Physical address of the frame to wich page is mapped.
205 * @param flags Different flags for the mapping.
[457d18a]206 */
[666773c]207void
208vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame,
209 int flags)
[457d18a]210{
[5bda2f3e]211 region_register_t rr_save, rr;
[98000fb]212 size_t vrn;
[457d18a]213 rid_t rid;
[7f1c620]214 uint64_t tag;
[457d18a]215
[63e27ef]216 assert(v);
[457d18a]217
218 vrn = page >> VRN_SHIFT;
219 rid = ASID2RID(asid, vrn);
[a35b458]220
[457d18a]221 /*
222 * Compute ttag.
223 */
224 rr_save.word = rr_read(vrn);
225 rr.word = rr_save.word;
226 rr.map.rid = rid;
227 rr_write(vrn, rr.word);
228 srlz_i();
229 tag = ttag(page);
230 rr_write(vrn, rr_save.word);
231 srlz_i();
232 srlz_d();
[a35b458]233
[457d18a]234 /*
235 * Clear the entry.
236 */
[c7ec94a4]237 v->word[0] = 0;
238 v->word[1] = 0;
239 v->word[2] = 0;
240 v->word[3] = 0;
[a35b458]241
[c7ec94a4]242 v->present.p = true;
[666773c]243 v->present.ma = (flags & PAGE_CACHEABLE) ?
244 MA_WRITEBACK : MA_UNCACHEABLE;
[5bda2f3e]245 v->present.a = false; /* not accessed */
246 v->present.d = false; /* not dirty */
[c7ec94a4]247 v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
248 v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
[1b20da0]249 v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
[c7ec94a4]250 v->present.ppn = frame >> PPN_SHIFT;
[5bda2f3e]251 v->present.ed = false; /* exception not deffered */
[c7ec94a4]252 v->present.ps = PAGE_WIDTH;
253 v->present.key = 0;
254 v->present.tag.tag_word = tag;
[457d18a]255}
[b45c443]256
[06e1e95]257/** @}
[b45c443]258 */
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