[6d7ffa65] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Jakub Jermar
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| 3 | * Copyright (c) 2006 Jakub Vana
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[6d7ffa65] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[c5429fe] | 30 | /** @addtogroup kernel_ia64_mm
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[b45c443] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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[6d7ffa65] | 36 | #include <arch/mm/page.h>
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[63e27ef] | 37 | #include <assert.h>
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[6d7ffa65] | 38 | #include <genarch/mm/page_ht.h>
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[c2b95d3] | 39 | #include <mm/asid.h>
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[457d18a] | 40 | #include <arch/mm/asid.h>
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[68091bd] | 41 | #include <arch/mm/vhpt.h>
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[d99c1d2] | 42 | #include <typedefs.h>
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[6d7ffa65] | 43 | #include <mm/page.h>
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[c2b95d3] | 44 | #include <mm/frame.h>
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[6d7ffa65] | 45 | #include <config.h>
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| 46 | #include <panic.h>
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[2a003d5b] | 47 | #include <arch/asm.h>
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[05882233] | 48 | #include <barrier.h>
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[59e4864] | 49 | #include <align.h>
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[6d7ffa65] | 50 |
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[c7ec94a4] | 51 | static void set_environment(void);
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[457d18a] | 52 |
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| 53 | /** Initialize ia64 virtual address translation subsystem. */
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| 54 | void page_arch_init(void)
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| 55 | {
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[f5935ed] | 56 | page_mapping_operations = &ht_mapping_operations;
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[457d18a] | 57 | pk_disable();
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[c7ec94a4] | 58 | set_environment();
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[457d18a] | 59 | }
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| 60 |
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[c2b95d3] | 61 | /** Initialize VHPT and region registers. */
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[c7ec94a4] | 62 | void set_environment(void)
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[fd537a0] | 63 | {
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[5bda2f3e] | 64 | region_register_t rr;
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| 65 | pta_register_t pta;
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[fd537a0] | 66 | int i;
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[e49e234] | 67 | #ifdef CONFIG_VHPT
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[7f1c620] | 68 | uintptr_t vhpt_base;
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[68091bd] | 69 | #endif
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[5ac2e61] | 70 |
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[c2b95d3] | 71 | /*
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[d9ee2ea] | 72 | * Set up kernel region registers.
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| 73 | * VRN_KERNEL has already been set in start.S.
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| 74 | * For paranoia reasons, we set it again.
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[c2b95d3] | 75 | */
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[18b6a88] | 76 | for (i = 0; i < REGION_REGISTERS; i++) {
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[9459255] | 77 | rr.word = rr_read(i);
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[849386a] | 78 | rr.map.ve = 0; /* disable VHPT walker */
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[d9ee2ea] | 79 | rr.map.rid = ASID2RID(ASID_KERNEL, i);
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[9ad03fe] | 80 | rr.map.ps = PAGE_WIDTH;
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[c2b95d3] | 81 | rr_write(i, rr.word);
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| 82 | srlz_i();
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| 83 | srlz_d();
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| 84 | }
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[6461d67c] | 85 |
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[1b20da0] | 86 | #ifdef CONFIG_VHPT
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[68091bd] | 87 | vhpt_base = vhpt_set_up();
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| 88 | #endif
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[c2b95d3] | 89 | /*
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| 90 | * Set up PTA register.
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| 91 | */
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| 92 | pta.word = pta_read();
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[68091bd] | 93 | #ifndef CONFIG_VHPT
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[c2b95d3] | 94 | pta.map.ve = 0; /* disable VHPT walker */
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[68091bd] | 95 | pta.map.base = 0 >> PTA_BASE_SHIFT;
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| 96 | #else
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| 97 | pta.map.ve = 1; /* enable VHPT walker */
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| 98 | pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
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| 99 | #endif
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[c2b95d3] | 100 | pta.map.vf = 1; /* large entry format */
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| 101 | pta.map.size = VHPT_WIDTH;
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| 102 | pta_write(pta.word);
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| 103 | srlz_i();
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| 104 | srlz_d();
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| 105 | }
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[fd537a0] | 106 |
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[849386a] | 107 | /** Calculate address of collision chain from VPN and ASID.
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| 108 | *
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[457d18a] | 109 | * Interrupts must be disabled.
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[849386a] | 110 | *
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[666773c] | 111 | * @param page Address of virtual page including VRN bits.
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| 112 | * @param asid Address space identifier.
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[849386a] | 113 | *
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[666773c] | 114 | * @return VHPT entry address.
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[849386a] | 115 | */
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[7f1c620] | 116 | vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
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[849386a] | 117 | {
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[5bda2f3e] | 118 | region_register_t rr_save, rr;
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[98000fb] | 119 | size_t vrn;
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[457d18a] | 120 | rid_t rid;
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[c7ec94a4] | 121 | vhpt_entry_t *v;
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[849386a] | 122 |
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[457d18a] | 123 | vrn = page >> VRN_SHIFT;
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| 124 | rid = ASID2RID(asid, vrn);
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[a35b458] | 125 |
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[457d18a] | 126 | rr_save.word = rr_read(vrn);
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| 127 | if (rr_save.map.rid == rid) {
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| 128 | /*
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| 129 | * The RID is already in place, compute thash and return.
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| 130 | */
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[c7ec94a4] | 131 | v = (vhpt_entry_t *) thash(page);
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| 132 | return v;
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[457d18a] | 133 | }
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[a35b458] | 134 |
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[457d18a] | 135 | /*
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| 136 | * The RID must be written to some region register.
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| 137 | * To speed things up, register indexed by vrn is used.
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| 138 | */
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[849386a] | 139 | rr.word = rr_save.word;
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[457d18a] | 140 | rr.map.rid = rid;
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| 141 | rr_write(vrn, rr.word);
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[849386a] | 142 | srlz_i();
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[c7ec94a4] | 143 | v = (vhpt_entry_t *) thash(page);
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[457d18a] | 144 | rr_write(vrn, rr_save.word);
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[849386a] | 145 | srlz_i();
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| 146 | srlz_d();
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| 147 |
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[c7ec94a4] | 148 | return v;
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[849386a] | 149 | }
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[457d18a] | 150 |
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| 151 | /** Compare ASID and VPN against PTE.
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| 152 | *
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| 153 | * Interrupts must be disabled.
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| 154 | *
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[666773c] | 155 | * @param page Address of virtual page including VRN bits.
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| 156 | * @param asid Address space identifier.
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[457d18a] | 157 | *
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[666773c] | 158 | * @return True if page and asid match the page and asid of t,
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| 159 | * false otherwise.
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[457d18a] | 160 | */
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[7f1c620] | 161 | bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
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[457d18a] | 162 | {
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[5bda2f3e] | 163 | region_register_t rr_save, rr;
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[98000fb] | 164 | size_t vrn;
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[457d18a] | 165 | rid_t rid;
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| 166 | bool match;
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| 167 |
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[63e27ef] | 168 | assert(v);
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[457d18a] | 169 |
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| 170 | vrn = page >> VRN_SHIFT;
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| 171 | rid = ASID2RID(asid, vrn);
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[a35b458] | 172 |
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[457d18a] | 173 | rr_save.word = rr_read(vrn);
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| 174 | if (rr_save.map.rid == rid) {
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| 175 | /*
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| 176 | * The RID is already in place, compare ttag with t and return.
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| 177 | */
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[c7ec94a4] | 178 | return ttag(page) == v->present.tag.tag_word;
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[457d18a] | 179 | }
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[a35b458] | 180 |
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[457d18a] | 181 | /*
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| 182 | * The RID must be written to some region register.
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| 183 | * To speed things up, register indexed by vrn is used.
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| 184 | */
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| 185 | rr.word = rr_save.word;
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| 186 | rr.map.rid = rid;
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| 187 | rr_write(vrn, rr.word);
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| 188 | srlz_i();
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[c7ec94a4] | 189 | match = (ttag(page) == v->present.tag.tag_word);
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[457d18a] | 190 | rr_write(vrn, rr_save.word);
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| 191 | srlz_i();
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| 192 | srlz_d();
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| 193 |
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[1b20da0] | 194 | return match;
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[457d18a] | 195 | }
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| 196 |
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| 197 | /** Set up one VHPT entry.
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| 198 | *
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[abbc16e] | 199 | * @param v VHPT entry to be set up.
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[666773c] | 200 | * @param page Virtual address of the page mapped by the entry.
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| 201 | * @param asid Address space identifier of the address space to which
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| 202 | * page belongs.
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| 203 | * @param frame Physical address of the frame to wich page is mapped.
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| 204 | * @param flags Different flags for the mapping.
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[457d18a] | 205 | */
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[666773c] | 206 | void
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| 207 | vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame,
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| 208 | int flags)
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[457d18a] | 209 | {
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[5bda2f3e] | 210 | region_register_t rr_save, rr;
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[98000fb] | 211 | size_t vrn;
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[457d18a] | 212 | rid_t rid;
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[7f1c620] | 213 | uint64_t tag;
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[457d18a] | 214 |
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[63e27ef] | 215 | assert(v);
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[457d18a] | 216 |
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| 217 | vrn = page >> VRN_SHIFT;
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| 218 | rid = ASID2RID(asid, vrn);
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[a35b458] | 219 |
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[457d18a] | 220 | /*
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| 221 | * Compute ttag.
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| 222 | */
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| 223 | rr_save.word = rr_read(vrn);
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| 224 | rr.word = rr_save.word;
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| 225 | rr.map.rid = rid;
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| 226 | rr_write(vrn, rr.word);
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| 227 | srlz_i();
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| 228 | tag = ttag(page);
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| 229 | rr_write(vrn, rr_save.word);
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| 230 | srlz_i();
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| 231 | srlz_d();
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[a35b458] | 232 |
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[457d18a] | 233 | /*
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| 234 | * Clear the entry.
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| 235 | */
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[c7ec94a4] | 236 | v->word[0] = 0;
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| 237 | v->word[1] = 0;
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| 238 | v->word[2] = 0;
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| 239 | v->word[3] = 0;
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[a35b458] | 240 |
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[c7ec94a4] | 241 | v->present.p = true;
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[666773c] | 242 | v->present.ma = (flags & PAGE_CACHEABLE) ?
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| 243 | MA_WRITEBACK : MA_UNCACHEABLE;
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[5bda2f3e] | 244 | v->present.a = false; /* not accessed */
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| 245 | v->present.d = false; /* not dirty */
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[c7ec94a4] | 246 | v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
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| 247 | v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
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[1b20da0] | 248 | v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
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[c7ec94a4] | 249 | v->present.ppn = frame >> PPN_SHIFT;
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[5bda2f3e] | 250 | v->present.ed = false; /* exception not deffered */
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[c7ec94a4] | 251 | v->present.ps = PAGE_WIDTH;
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| 252 | v->present.key = 0;
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| 253 | v->present.tag.tag_word = tag;
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[457d18a] | 254 | }
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[b45c443] | 255 |
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[06e1e95] | 256 | /** @}
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[b45c443] | 257 | */
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