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Last change on this file since 15b6715 was 293703e, checked in by Jakub Jermar <jakub@…>, 11 years ago
Autogenerate ia64 istate_t and its offsets.
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File size: 17.7 KB

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[d2bb9f8a]	1	#
[df4ed85]	2	# Copyright (c) 2005 Jakub Vana
	3	# Copyright (c) 2005 Jakub Jermar
[d2bb9f8a]	4	# All rights reserved.
	5	#
	6	# Redistribution and use in source and binary forms, with or without
	7	# modification, are permitted provided that the following conditions
	8	# are met:
	9	#
	10	# - Redistributions of source code must retain the above copyright
	11	# notice, this list of conditions and the following disclaimer.
	12	# - Redistributions in binary form must reproduce the above copyright
	13	# notice, this list of conditions and the following disclaimer in the
	14	# documentation and/or other materials provided with the distribution.
	15	# - The name of the author may not be used to endorse or promote products
	16	# derived from this software without specific prior written permission.
	17	#
	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	#
	29
[17a20bc]	30	#include <arch/stack.h>
[8a0b3730]	31	#include <arch/register.h>
[83d2d0e]	32	#include <arch/mm/page.h>
[293703e]	33	#include <arch/istate_struct.h>
[83d2d0e]	34	#include <align.h>
[17a20bc]	35
[293703e]	36	#define STACK_FRAME_SIZE ALIGN_UP(ISTATE_SIZE + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
[17a20bc]	37
[293703e]	38	#define FLOAT_ITEM_SIZE (STACK_ITEM_SIZE * 2)
[d2bb9f8a]	39
[bc314be8]	40	/** Partitioning of bank 0 registers. */
	41	#define R_OFFS r16
	42	#define R_HANDLER r17
	43	#define R_RET r18
[901122b]	44	#define R_TMP r19
[cd373bb]	45	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
[bc314be8]	46	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
	47
[7b712b60]	48	/* Speculation vector handler */
	49	.macro SPECULATION_VECTOR_HANDLER offs
	50	.org ivt + \offs
	51
	52	/* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
	53	mov r16 = pr
	54	mov r17 = cr.iim
	55	mov r18 = cr.iip
	56	mov r19 = cr.ipsr
	57	mov r20 = cr.isr ;;
	58
	59	/* 2. Move IIP to IIPA. */
	60	mov cr.iipa = r18
	61
	62	/* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
	63	shl r17 = r17, 43 ;; /* shift bit 20 to bit 63 */
	64	shr r17 = r17, 39 ;; /* signed shift right to bit 24 */
	65	add r18 = r18, r17 ;;
	66	mov cr.iip = r18
	67
	68	/* 4. Set IPSR.ri to 0. */
	69	dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
	70	mov cr.ipsr = r19
	71
	72	/* 5. Check whether IPSR.tb or IPSR.ss is set. */
	73
	74	/* TODO:
	75	* Implement this when Taken Branch and Single Step traps can occur.
	76	*/
	77
	78	/* 6. Restore predicates and return from interruption. */
	79	mov pr = r16 ;;
	80	rfi
	81	.endm
	82
[2262044]	83	/** Heavyweight interrupt handler
	84	*
[154049e]	85	* This macro roughly follows steps from 1 to 19 described in
	86	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
	87	*
[2262044]	88	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
	89	* This goal is achieved by using procedure calls after RSE becomes operational.
	90	*
[154049e]	91	* Some steps are skipped (enabling and disabling interrupts).
[5b65205]	92	*
	93	* @param offs Offset from the beginning of IVT.
	94	* @param handler Interrupt handler address.
[154049e]	95	*/
[e2ec980f]	96	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
	97	.org ivt + \offs
[bc314be8]	98	mov R_OFFS = \offs
	99	movl R_HANDLER = \handler ;;
[e2ec980f]	100	br heavyweight_handler
	101	.endm
[154049e]	102
[e2ec980f]	103	.global heavyweight_handler
	104	heavyweight_handler:
[154049e]	105	/* 1. copy interrupt registers into bank 0 */
[bc314be8]	106
	107	/*
[83d2d0e]	108	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
[bc314be8]	109	*/
[41fa6f2]	110
[2ba1f39]	111	/* Set up FPU as in interrupted context. */
	112	mov r24 = psr
	113	mov r25 = cr.ipsr
	114	mov r26 = PSR_DFH_MASK
	115	mov r27 = ~PSR_DFH_MASK ;;
	116	and r26 = r25, r26
[293703e]	117	and r24 = r24, r27 ;;
	118	or r24 = r24, r26 ;;
	119	mov psr.l = r24 ;;
[41fa6f2]	120	srlz.i
[293703e]	121	srlz.d ;;
[41fa6f2]	122
[154049e]	123	mov r24 = cr.iip
	124	mov r25 = cr.ipsr
	125	mov r26 = cr.iipa
	126	mov r27 = cr.isr
	127	mov r28 = cr.ifa
	128
	129	/* 2. preserve predicate register into bank 0 */
	130	mov r29 = pr ;;
	131
[2262044]	132	/* 3. switch to kernel memory stack */
[83d2d0e]	133	mov r30 = cr.ipsr
[cd373bb]	134	shr.u r31 = r12, VRN_SHIFT ;;
	135
	136	shr.u r30 = r30, PSR_CPL_SHIFT ;;
	137	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
[83d2d0e]	138
	139	/*
[cd373bb]	140	* Set p3 to true if the interrupted context executed in kernel mode.
	141	* Set p4 to false if the interrupted context didn't execute in kernel mode.
[83d2d0e]	142	*/
[cd373bb]	143	cmp.eq p3, p4 = r30, r0 ;;
	144	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
[83d2d0e]	145
	146	/*
[cd373bb]	147	* Set p3 to true if the stack register references kernel address space.
	148	* Set p4 to false if the stack register doesn't reference kernel address space.
[83d2d0e]	149	*/
[901122b]	150	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
[83d2d0e]	151
	152	/*
[cd373bb]	153	* Now, p4 is true iff the stack needs to be switched to kernel stack.
[83d2d0e]	154	*/
	155	mov r30 = r12
[901122b]	156	(p4) mov r12 = R_KSTACK ;;
[83d2d0e]	157
[293703e]	158	add r12 = -STACK_FRAME_SIZE, r12 ;;
	159	add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_IN6, r12
[e2ec980f]	160
[901122b]	161	/* 4. save registers in bank 0 into memory stack */
	162
	163	/*
	164	* If this is break_instruction handler,
	165	* copy input parameters to stack.
	166	*/
	167	mov R_TMP = 0x2c00 ;;
[1b03ed3]	168	cmp.eq p6, p5 = R_OFFS, R_TMP ;;
[901122b]	169
	170	/*
[1b03ed3]	171	* From now on, if this is break_instruction handler, p6 is true and p5
	172	* is false. Otherwise p6 is false and p5 is true.
[901122b]	173	* Note that p5 is a preserved predicate register and we make use of it.
	174	*/
[5c089c3a]	175
[293703e]	176	(p6) st8 [r31] = r38, -STACK_ITEM_SIZE ;; /* save in6 */
	177	(p6) st8 [r31] = r37, -STACK_ITEM_SIZE ;; /* save in5 */
	178	(p6) st8 [r31] = r36, -STACK_ITEM_SIZE ;; /* save in4 */
	179	(p6) st8 [r31] = r35, -STACK_ITEM_SIZE ;; /* save in3 */
	180	(p6) st8 [r31] = r34, -STACK_ITEM_SIZE ;; /* save in2 */
	181	(p6) st8 [r31] = r33, -STACK_ITEM_SIZE ;; /* save in1 */
	182	(p6) st8 [r31] = r32, -STACK_ITEM_SIZE ;; /* save in0 */
	183	(p5) add r31 = -(7 * STACK_ITEM_SIZE), r31 ;;
[901122b]	184
[293703e]	185	st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save old stack pointer */
[83d2d0e]	186
[293703e]	187	st8 [r31] = r29, -STACK_ITEM_SIZE ;; /* save predicate registers */
[2262044]	188
[293703e]	189	st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save cr.iip */
	190	st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save cr.ipsr */
	191	st8 [r31] = r26, -STACK_ITEM_SIZE ;; /* save cr.iipa */
	192	st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save cr.isr */
	193	st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save cr.ifa */
[2262044]	194
	195	/* 5. RSE switch from interrupted context */
[154049e]	196	mov r24 = ar.rsc
	197	mov r25 = ar.pfs
	198	cover
	199	mov r26 = cr.ifs
	200
[293703e]	201	st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save ar.rsc */
	202	st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save ar.pfs */
	203	st8 [r31] = r26, -STACK_ITEM_SIZE /* save ar.ifs */
[154049e]	204
[b994a60]	205	and r24 = ~(RSC_PL_MASK), r24 ;;
	206	and r30 = ~(RSC_MODE_MASK), r24 ;;
	207	mov ar.rsc = r30 ;; /* update RSE state */
[154049e]	208
	209	mov r27 = ar.rnat
[e2ec980f]	210	mov r28 = ar.bspstore ;;
[154049e]	211
[cd373bb]	212	/*
[1b03ed3]	213	* Inspect BSPSTORE to figure out whether it is necessary to switch to
	214	* kernel BSPSTORE.
[cd373bb]	215	*/
[901122b]	216	(p1) shr.u r30 = r28, VRN_SHIFT ;;
	217	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
[cd373bb]	218
	219	/*
	220	* If BSPSTORE needs to be switched, p1 is false and p2 is true.
	221	*/
[901122b]	222	(p1) mov r30 = r28
	223	(p2) mov r30 = R_KSTACK_BSP ;;
	224	(p2) mov ar.bspstore = r30 ;;
[154049e]	225
	226	mov r29 = ar.bsp
	227
[293703e]	228	st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save ar.rnat */
	229	st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save new value written to ar.bspstore */
	230	st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save ar.bspstore */
	231	st8 [r31] = r29, -STACK_ITEM_SIZE /* save ar.bsp */
[154049e]	232
[b994a60]	233	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
[154049e]	234
[e2ec980f]	235	/* steps 6 - 15 are done by heavyweight_handler_inner() */
[cd373bb]	236	mov R_RET = b0 /* save b0 belonging to interrupted context */
[bc314be8]	237	br.call.sptk.many b0 = heavyweight_handler_inner
[cd373bb]	238	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
[2262044]	239
[e2ec980f]	240	/* 16. RSE switch to interrupted context */
[1b03ed3]	241	cover /* allocate zero size frame (step 1 (from Intel Docs)) */
[e2ec980f]	242
[293703e]	243	add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_AR_BSP, r12 ;;
[e2ec980f]	244
[293703e]	245	ld8 r30 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bsp */
	246	ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bspstore */
	247	ld8 r28 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bspstore_new */
[e1c68e0c]	248	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
[e2ec980f]	249	shl r27 = r27, 16
	250
	251	mov r24 = ar.rsc ;;
	252	and r30 = ~3, r24 ;;
	253	or r24 = r30 , r27 ;;
	254	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
	255
	256	loadrs /* (step 3) */
	257
[293703e]	258	ld8 r27 = [r31], +STACK_ITEM_SIZE ;; /* load ar.rnat */
	259	ld8 r26 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ifs */
	260	ld8 r25 = [r31], +STACK_ITEM_SIZE ;; /* load ar.pfs */
	261	ld8 r24 = [r31], +STACK_ITEM_SIZE ;; /* load ar.rsc */
[e2ec980f]	262
[e1c68e0c]	263	mov ar.bspstore = r29 ;; /* (step 4) */
	264	mov ar.rnat = r27 /* (step 5) */
[e2ec980f]	265
	266	mov ar.pfs = r25 /* (step 6) */
	267	mov cr.ifs = r26
	268
	269	mov ar.rsc = r24 /* (step 7) */
	270
	271	/* 17. restore interruption state from memory stack */
[293703e]	272	ld8 r28 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ifa */
	273	ld8 r27 = [r31], +STACK_ITEM_SIZE ;; /* load cr.isr */
	274	ld8 r26 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iipa */
	275	ld8 r25 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ipsr */
	276	ld8 r24 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iip */
[e2ec980f]	277
[41fa6f2]	278	mov cr.iip = r24;;
[e2ec980f]	279	mov cr.iipa = r26
	280	mov cr.isr = r27
	281	mov cr.ifa = r28
[2ba1f39]	282
	283	/* Set up FPU as in exception. */
	284	mov r24 = psr
	285	mov r26 = PSR_DFH_MASK
	286	mov r27 = ~PSR_DFH_MASK ;;
	287	and r25 = r25, r27
	288	and r24 = r24, r26 ;;
[293703e]	289	or r25 = r25, r24 ;;
[41fa6f2]	290	mov cr.ipsr = r25
[e2ec980f]	291
	292	/* 18. restore predicate registers from memory stack */
[293703e]	293	ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load predicate registers */
[e2ec980f]	294	mov pr = r29
	295
	296	/* 19. return from interruption */
[293703e]	297	ld8 r12 = [r31] /* load stack pointer */
[e2ec980f]	298	rfi ;;
[2262044]	299
	300	.global heavyweight_handler_inner
	301	heavyweight_handler_inner:
	302	/*
	303	* From this point, the rest of the interrupted context
	304	* will be preserved in stacked registers and backing store.
	305	*/
[5581c45e]	306	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
[2262044]	307
[e2ec980f]	308	/* bank 0 is going to be shadowed, copy essential data from there */
[bc314be8]	309	mov loc1 = R_RET /* b0 belonging to interrupted context */
	310	mov loc2 = R_HANDLER
	311	mov out0 = R_OFFS
[e2ec980f]	312
	313	add out1 = STACK_SCRATCH_AREA_SIZE, r12
[2262044]	314
[154049e]	315	/* 6. switch to bank 1 and reenable PSR.ic */
[8a0b3730]	316	ssm PSR_IC_MASK
[154049e]	317	bsw.1 ;;
	318	srlz.d
	319
	320	/* 7. preserve branch and application registers */
[e2ec980f]	321	mov loc3 = ar.unat
	322	mov loc4 = ar.lc
	323	mov loc5 = ar.ec
	324	mov loc6 = ar.ccv
	325	mov loc7 = ar.csd
	326	mov loc8 = ar.ssd
[2262044]	327
[e2ec980f]	328	mov loc9 = b0
	329	mov loc10 = b1
	330	mov loc11 = b2
	331	mov loc12 = b3
	332	mov loc13 = b4
	333	mov loc14 = b5
	334	mov loc15 = b6
	335	mov loc16 = b7
[154049e]	336
	337	/* 8. preserve general and floating-point registers */
[e2ec980f]	338	mov loc17 = r1
	339	mov loc18 = r2
	340	mov loc19 = r3
	341	mov loc20 = r4
	342	mov loc21 = r5
	343	mov loc22 = r6
	344	mov loc23 = r7
[901122b]	345	(p5) mov loc24 = r8 /* only if not in break_instruction handler */
[e2ec980f]	346	mov loc25 = r9
	347	mov loc26 = r10
	348	mov loc27 = r11
[2262044]	349	/* skip r12 (stack pointer) */
[e2ec980f]	350	mov loc28 = r13
	351	mov loc29 = r14
	352	mov loc30 = r15
	353	mov loc31 = r16
	354	mov loc32 = r17
	355	mov loc33 = r18
	356	mov loc34 = r19
	357	mov loc35 = r20
	358	mov loc36 = r21
	359	mov loc37 = r22
	360	mov loc38 = r23
	361	mov loc39 = r24
	362	mov loc40 = r25
	363	mov loc41 = r26
	364	mov loc42 = r27
	365	mov loc43 = r28
	366	mov loc44 = r29
	367	mov loc45 = r30
	368	mov loc46 = r31
[5581c45e]	369
[293703e]	370	add r24 = ISTATE_OFFSET_F8 + STACK_SCRATCH_AREA_SIZE, r12
	371	add r25 = ISTATE_OFFSET_F9 + STACK_SCRATCH_AREA_SIZE, r12
	372	add r26 = ISTATE_OFFSET_F2 + STACK_SCRATCH_AREA_SIZE, r12
	373	add r27 = ISTATE_OFFSET_F3 + STACK_SCRATCH_AREA_SIZE, r12
	374	add r28 = ISTATE_OFFSET_F4 + STACK_SCRATCH_AREA_SIZE, r12
	375	add r29 = ISTATE_OFFSET_F5 + STACK_SCRATCH_AREA_SIZE, r12
	376	add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
	377	add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
[2ba1f39]	378
[293703e]	379	stf.spill [r26] = f2, 8 * FLOAT_ITEM_SIZE
	380	stf.spill [r27] = f3, 8 * FLOAT_ITEM_SIZE
	381	stf.spill [r28] = f4, 8 * FLOAT_ITEM_SIZE
	382	stf.spill [r29] = f5, 8 * FLOAT_ITEM_SIZE
	383	stf.spill [r30] = f6, 8 * FLOAT_ITEM_SIZE
	384	stf.spill [r31] = f7, 8 * FLOAT_ITEM_SIZE ;;
	385
	386	stf.spill [r24] = f8, 8 * FLOAT_ITEM_SIZE
	387	stf.spill [r25] = f9, 8 * FLOAT_ITEM_SIZE
	388	stf.spill [r26] = f10, 8 * FLOAT_ITEM_SIZE
	389	stf.spill [r27] = f11, 8 * FLOAT_ITEM_SIZE
	390	stf.spill [r28] = f12, 8 * FLOAT_ITEM_SIZE
	391	stf.spill [r29] = f13, 8 * FLOAT_ITEM_SIZE
	392	stf.spill [r30] = f14, 8 * FLOAT_ITEM_SIZE
	393	stf.spill [r31] = f15, 8 * FLOAT_ITEM_SIZE ;;
	394
	395	stf.spill [r24] = f16, 8 * FLOAT_ITEM_SIZE
	396	stf.spill [r25] = f17, 8 * FLOAT_ITEM_SIZE
	397	stf.spill [r26] = f18, 8 * FLOAT_ITEM_SIZE
	398	stf.spill [r27] = f19, 8 * FLOAT_ITEM_SIZE
	399	stf.spill [r28] = f20, 8 * FLOAT_ITEM_SIZE
	400	stf.spill [r29] = f21, 8 * FLOAT_ITEM_SIZE
	401	stf.spill [r30] = f22, 8 * FLOAT_ITEM_SIZE
	402	stf.spill [r31] = f23, 8 * FLOAT_ITEM_SIZE ;;
	403
	404	stf.spill [r24] = f24
	405	stf.spill [r25] = f25
	406	stf.spill [r26] = f26
	407	stf.spill [r27] = f27
	408	stf.spill [r28] = f28
	409	stf.spill [r29] = f29
	410	stf.spill [r30] = f30
	411	stf.spill [r31] = f31 ;;
[2ba1f39]	412
	413	mov loc47 = ar.fpsr /* preserve floating point status register */
[2262044]	414
[154049e]	415	/* 9. skipped (will not enable interrupts) */
[8a0b3730]	416	/*
	417	* ssm PSR_I_MASK
	418	* ;;
	419	* srlz.d
	420	*/
[154049e]	421
[2262044]	422	/* 10. call handler */
[18ba2e4f]	423	movl r1 = __gp
[b994a60]	424
[e2ec980f]	425	mov b1 = loc2
[2262044]	426	br.call.sptk.many b0 = b1
	427
	428	/* 11. return from handler */
	429	0:
[154049e]	430
[2262044]	431	/* 12. skipped (will not disable interrupts) */
[8a0b3730]	432	/*
	433	* rsm PSR_I_MASK
	434	* ;;
	435	* srlz.d
	436	*/
[2262044]	437
[154049e]	438	/* 13. restore general and floating-point registers */
[293703e]	439	add r24 = ISTATE_OFFSET_F8 + STACK_SCRATCH_AREA_SIZE, r12
	440	add r25 = ISTATE_OFFSET_F9 + STACK_SCRATCH_AREA_SIZE, r12
	441	add r26 = ISTATE_OFFSET_F2 + STACK_SCRATCH_AREA_SIZE, r12
	442	add r27 = ISTATE_OFFSET_F3 + STACK_SCRATCH_AREA_SIZE, r12
	443	add r28 = ISTATE_OFFSET_F4 + STACK_SCRATCH_AREA_SIZE, r12
	444	add r29 = ISTATE_OFFSET_F5 + STACK_SCRATCH_AREA_SIZE, r12
	445	add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
	446	add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
	447
	448	ldf.fill f2 = [r26], 8 * FLOAT_ITEM_SIZE
	449	ldf.fill f3 = [r27], 8 * FLOAT_ITEM_SIZE
	450	ldf.fill f4 = [r28], 8 * FLOAT_ITEM_SIZE
	451	ldf.fill f5 = [r29], 8 * FLOAT_ITEM_SIZE
	452	ldf.fill f6 = [r30], 8 * FLOAT_ITEM_SIZE
	453	ldf.fill f7 = [r31], 8 * FLOAT_ITEM_SIZE ;;
	454
	455	ldf.fill f8 = [r24], 8 * FLOAT_ITEM_SIZE
	456	ldf.fill f9 = [r25], 8 * FLOAT_ITEM_SIZE
	457	ldf.fill f10 = [r26],8 * FLOAT_ITEM_SIZE
	458	ldf.fill f11 = [r27], 8 * FLOAT_ITEM_SIZE
	459	ldf.fill f12 = [r28], 8 * FLOAT_ITEM_SIZE
	460	ldf.fill f13 = [r29], 8 * FLOAT_ITEM_SIZE
	461	ldf.fill f14 = [r30], 8 * FLOAT_ITEM_SIZE
	462	ldf.fill f15 = [r31], 8 * FLOAT_ITEM_SIZE ;;
	463
	464	ldf.fill f16 = [r24], 8 * FLOAT_ITEM_SIZE
	465	ldf.fill f17 = [r25], 8 * FLOAT_ITEM_SIZE
	466	ldf.fill f18 = [r26], 8 * FLOAT_ITEM_SIZE
	467	ldf.fill f19 = [r27], 8 * FLOAT_ITEM_SIZE
	468	ldf.fill f20 = [r28], 8 * FLOAT_ITEM_SIZE
	469	ldf.fill f21 = [r29], 8 * FLOAT_ITEM_SIZE
	470	ldf.fill f22 = [r30], 8 * FLOAT_ITEM_SIZE
	471	ldf.fill f23 = [r31], 8 * FLOAT_ITEM_SIZE ;;
	472
	473	ldf.fill f24 = [r24]
	474	ldf.fill f25 = [r25]
	475	ldf.fill f26 = [r26]
	476	ldf.fill f27 = [r27]
	477	ldf.fill f28 = [r28]
	478	ldf.fill f29 = [r29]
	479	ldf.fill f30 = [r30]
	480	ldf.fill f31 = [r31] ;;
[41fa6f2]	481
[e2ec980f]	482	mov r1 = loc17
	483	mov r2 = loc18
	484	mov r3 = loc19
	485	mov r4 = loc20
	486	mov r5 = loc21
	487	mov r6 = loc22
	488	mov r7 = loc23
[901122b]	489	(p5) mov r8 = loc24 /* only if not in break_instruction handler */
[e2ec980f]	490	mov r9 = loc25
	491	mov r10 = loc26
	492	mov r11 = loc27
[2262044]	493	/* skip r12 (stack pointer) */
[e2ec980f]	494	mov r13 = loc28
	495	mov r14 = loc29
	496	mov r15 = loc30
	497	mov r16 = loc31
	498	mov r17 = loc32
	499	mov r18 = loc33
	500	mov r19 = loc34
	501	mov r20 = loc35
	502	mov r21 = loc36
	503	mov r22 = loc37
	504	mov r23 = loc38
	505	mov r24 = loc39
	506	mov r25 = loc40
	507	mov r26 = loc41
	508	mov r27 = loc42
	509	mov r28 = loc43
	510	mov r29 = loc44
	511	mov r30 = loc45
	512	mov r31 = loc46
[2ba1f39]	513
	514	mov ar.fpsr = loc47 /* restore floating point status register */
[5581c45e]	515
[154049e]	516	/* 14. restore branch and application registers */
[e2ec980f]	517	mov ar.unat = loc3
	518	mov ar.lc = loc4
	519	mov ar.ec = loc5
	520	mov ar.ccv = loc6
	521	mov ar.csd = loc7
	522	mov ar.ssd = loc8
[2262044]	523
[e2ec980f]	524	mov b0 = loc9
	525	mov b1 = loc10
	526	mov b2 = loc11
	527	mov b3 = loc12
	528	mov b4 = loc13
	529	mov b5 = loc14
	530	mov b6 = loc15
	531	mov b7 = loc16
[154049e]	532
	533	/* 15. disable PSR.ic and switch to bank 0 */
[8a0b3730]	534	rsm PSR_IC_MASK
[154049e]	535	bsw.0 ;;
	536	srlz.d
[2262044]	537
[bc314be8]	538	mov R_RET = loc1
[2262044]	539	mov ar.pfs = loc0
[e2ec980f]	540	br.ret.sptk.many b0
[d2bb9f8a]	541
[e2ec980f]	542	.global ivt
[d2bb9f8a]	543	.align 32768
[e2ec980f]	544	ivt:
	545	HEAVYWEIGHT_HANDLER 0x0000
	546	HEAVYWEIGHT_HANDLER 0x0400
	547	HEAVYWEIGHT_HANDLER 0x0800
[95042fd]	548	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	549	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	550	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
[e2ec980f]	551	HEAVYWEIGHT_HANDLER 0x1800
	552	HEAVYWEIGHT_HANDLER 0x1c00
[95042fd]	553	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	554	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	555	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
[e2ec980f]	556	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	557	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
	558	HEAVYWEIGHT_HANDLER 0x3400
	559	HEAVYWEIGHT_HANDLER 0x3800
	560	HEAVYWEIGHT_HANDLER 0x3c00
	561	HEAVYWEIGHT_HANDLER 0x4000
	562	HEAVYWEIGHT_HANDLER 0x4400
	563	HEAVYWEIGHT_HANDLER 0x4800
	564	HEAVYWEIGHT_HANDLER 0x4c00
	565
[95042fd]	566	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
[e2ec980f]	567	HEAVYWEIGHT_HANDLER 0x5100
	568	HEAVYWEIGHT_HANDLER 0x5200
[925be4e]	569	HEAVYWEIGHT_HANDLER 0x5300 data_access_rights_fault
[e2ec980f]	570	HEAVYWEIGHT_HANDLER 0x5400 general_exception
[9e1c942]	571	HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
[e2ec980f]	572	HEAVYWEIGHT_HANDLER 0x5600
[7b712b60]	573	SPECULATION_VECTOR_HANDLER 0x5700
[e2ec980f]	574	HEAVYWEIGHT_HANDLER 0x5800
	575	HEAVYWEIGHT_HANDLER 0x5900
	576	HEAVYWEIGHT_HANDLER 0x5a00
	577	HEAVYWEIGHT_HANDLER 0x5b00
	578	HEAVYWEIGHT_HANDLER 0x5c00
[9e1c942]	579	HEAVYWEIGHT_HANDLER 0x5d00
[e2ec980f]	580	HEAVYWEIGHT_HANDLER 0x5e00
	581	HEAVYWEIGHT_HANDLER 0x5f00
	582
	583	HEAVYWEIGHT_HANDLER 0x6000
	584	HEAVYWEIGHT_HANDLER 0x6100
	585	HEAVYWEIGHT_HANDLER 0x6200
	586	HEAVYWEIGHT_HANDLER 0x6300
	587	HEAVYWEIGHT_HANDLER 0x6400
	588	HEAVYWEIGHT_HANDLER 0x6500
	589	HEAVYWEIGHT_HANDLER 0x6600
	590	HEAVYWEIGHT_HANDLER 0x6700
	591	HEAVYWEIGHT_HANDLER 0x6800
	592	HEAVYWEIGHT_HANDLER 0x6900
	593	HEAVYWEIGHT_HANDLER 0x6a00
	594	HEAVYWEIGHT_HANDLER 0x6b00
	595	HEAVYWEIGHT_HANDLER 0x6c00
	596	HEAVYWEIGHT_HANDLER 0x6d00
	597	HEAVYWEIGHT_HANDLER 0x6e00
	598	HEAVYWEIGHT_HANDLER 0x6f00
	599
	600	HEAVYWEIGHT_HANDLER 0x7000
	601	HEAVYWEIGHT_HANDLER 0x7100
	602	HEAVYWEIGHT_HANDLER 0x7200
	603	HEAVYWEIGHT_HANDLER 0x7300
	604	HEAVYWEIGHT_HANDLER 0x7400
	605	HEAVYWEIGHT_HANDLER 0x7500
	606	HEAVYWEIGHT_HANDLER 0x7600
	607	HEAVYWEIGHT_HANDLER 0x7700
	608	HEAVYWEIGHT_HANDLER 0x7800
	609	HEAVYWEIGHT_HANDLER 0x7900
	610	HEAVYWEIGHT_HANDLER 0x7a00
	611	HEAVYWEIGHT_HANDLER 0x7b00
	612	HEAVYWEIGHT_HANDLER 0x7c00
	613	HEAVYWEIGHT_HANDLER 0x7d00
	614	HEAVYWEIGHT_HANDLER 0x7e00
	615	HEAVYWEIGHT_HANDLER 0x7f00

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