| 1 | #
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| 2 | # Copyright (c) 2005 Jakub Vana
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| 3 | # Copyright (c) 2005 Jakub Jermar
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| 4 | # All rights reserved.
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| 5 | #
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| 6 | # Redistribution and use in source and binary forms, with or without
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| 7 | # modification, are permitted provided that the following conditions
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| 8 | # are met:
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| 9 | #
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| 10 | # - Redistributions of source code must retain the above copyright
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| 11 | # notice, this list of conditions and the following disclaimer.
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| 12 | # - Redistributions in binary form must reproduce the above copyright
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| 13 | # notice, this list of conditions and the following disclaimer in the
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| 14 | # documentation and/or other materials provided with the distribution.
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| 15 | # - The name of the author may not be used to endorse or promote products
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| 16 | # derived from this software without specific prior written permission.
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| 17 | #
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| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | #
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| 29 |
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| 30 | #include <arch/stack.h>
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| 31 | #include <arch/register.h>
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| 32 | #include <arch/mm/page.h>
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| 33 | #include <arch/istate_struct.h>
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| 34 | #include <align.h>
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| 35 |
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| 36 | #define STACK_FRAME_SIZE ALIGN_UP(ISTATE_SIZE + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
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| 37 |
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| 38 | #define FLOAT_ITEM_SIZE (STACK_ITEM_SIZE * 2)
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| 39 |
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| 40 | /** Partitioning of bank 0 registers. */
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| 41 | #define R_OFFS r16
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| 42 | #define R_HANDLER r17
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| 43 | #define R_RET r18
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| 44 | #define R_TMP r19
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| 45 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
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| 46 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
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| 47 |
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| 48 | /* Speculation vector handler */
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| 49 | .macro SPECULATION_VECTOR_HANDLER offs
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| 50 | .org ivt + \offs
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| 51 |
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| 52 | /* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
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| 53 | mov r16 = pr
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| 54 | mov r17 = cr.iim
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| 55 | mov r18 = cr.iip
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| 56 | mov r19 = cr.ipsr
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| 57 | mov r20 = cr.isr ;;
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| 58 |
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| 59 | /* 2. Move IIP to IIPA. */
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| 60 | mov cr.iipa = r18
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| 61 |
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| 62 | /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
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| 63 | shl r17 = r17, 43 ;; /* shift bit 20 to bit 63 */
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| 64 | shr r17 = r17, 39 ;; /* signed shift right to bit 24 */
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| 65 | add r18 = r18, r17 ;;
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| 66 | mov cr.iip = r18
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| 67 |
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| 68 | /* 4. Set IPSR.ri to 0. */
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| 69 | dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
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| 70 | mov cr.ipsr = r19
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| 71 |
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| 72 | /* 5. Check whether IPSR.tb or IPSR.ss is set. */
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| 73 |
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| 74 | /* TODO:
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| 75 | * Implement this when Taken Branch and Single Step traps can occur.
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| 76 | */
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| 77 |
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| 78 | /* 6. Restore predicates and return from interruption. */
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| 79 | mov pr = r16 ;;
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| 80 | rfi
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| 81 | .endm
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| 82 |
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| 83 | /** Heavyweight interrupt handler
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| 84 | *
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| 85 | * This macro roughly follows steps from 1 to 19 described in
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| 86 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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| 87 | *
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| 88 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
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| 89 | * This goal is achieved by using procedure calls after RSE becomes operational.
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| 90 | *
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| 91 | * Some steps are skipped (enabling and disabling interrupts).
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| 92 | *
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| 93 | * @param offs Offset from the beginning of IVT.
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| 94 | * @param handler Interrupt handler address.
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| 95 | */
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| 96 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
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| 97 | .org ivt + \offs
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| 98 | mov R_OFFS = \offs
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| 99 | movl R_HANDLER = \handler ;;
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| 100 | br heavyweight_handler
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| 101 | .endm
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| 102 |
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| 103 | .global heavyweight_handler
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| 104 | heavyweight_handler:
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| 105 | /* 1. copy interrupt registers into bank 0 */
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| 106 |
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| 107 | /*
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| 108 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
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| 109 | */
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| 110 |
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| 111 | /* Set up FPU as in interrupted context. */
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| 112 | mov r24 = psr
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| 113 | mov r25 = cr.ipsr
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| 114 | mov r26 = PSR_DFH_MASK
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| 115 | mov r27 = ~PSR_DFH_MASK ;;
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| 116 | and r26 = r25, r26
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| 117 | and r24 = r24, r27 ;;
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| 118 | or r24 = r24, r26 ;;
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| 119 | mov psr.l = r24 ;;
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| 120 | srlz.i
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| 121 | srlz.d ;;
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| 122 |
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| 123 | mov r24 = cr.iip
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| 124 | mov r25 = cr.ipsr
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| 125 | mov r26 = cr.iipa
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| 126 | mov r27 = cr.isr
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| 127 | mov r28 = cr.ifa
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| 128 |
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| 129 | /* 2. preserve predicate register into bank 0 */
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| 130 | mov r29 = pr ;;
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| 131 |
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| 132 | /* 3. switch to kernel memory stack */
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| 133 | mov r30 = cr.ipsr
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| 134 | shr.u r31 = r12, VRN_SHIFT ;;
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| 135 |
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| 136 | shr.u r30 = r30, PSR_CPL_SHIFT ;;
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| 137 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
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| 138 |
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| 139 | /*
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| 140 | * Set p3 to true if the interrupted context executed in kernel mode.
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| 141 | * Set p4 to false if the interrupted context didn't execute in kernel mode.
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| 142 | */
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| 143 | cmp.eq p3, p4 = r30, r0 ;;
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| 144 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
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| 145 |
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| 146 | /*
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| 147 | * Set p3 to true if the stack register references kernel address space.
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| 148 | * Set p4 to false if the stack register doesn't reference kernel address space.
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| 149 | */
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| 150 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
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| 151 |
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| 152 | /*
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| 153 | * Now, p4 is true iff the stack needs to be switched to kernel stack.
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| 154 | */
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| 155 | mov r30 = r12
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| 156 | (p4) mov r12 = R_KSTACK ;;
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| 157 |
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| 158 | add r12 = -STACK_FRAME_SIZE, r12 ;;
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| 159 | add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_IN6, r12
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| 160 |
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| 161 | /* 4. save registers in bank 0 into memory stack */
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| 162 |
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| 163 | /*
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| 164 | * If this is break_instruction handler,
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| 165 | * copy input parameters to stack.
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| 166 | */
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| 167 | mov R_TMP = 0x2c00 ;;
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| 168 | cmp.eq p6, p5 = R_OFFS, R_TMP ;;
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| 169 |
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| 170 | /*
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| 171 | * From now on, if this is break_instruction handler, p6 is true and p5
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| 172 | * is false. Otherwise p6 is false and p5 is true.
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| 173 | * Note that p5 is a preserved predicate register and we make use of it.
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| 174 | */
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| 175 |
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| 176 | (p6) st8 [r31] = r38, -STACK_ITEM_SIZE ;; /* save in6 */
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| 177 | (p6) st8 [r31] = r37, -STACK_ITEM_SIZE ;; /* save in5 */
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| 178 | (p6) st8 [r31] = r36, -STACK_ITEM_SIZE ;; /* save in4 */
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| 179 | (p6) st8 [r31] = r35, -STACK_ITEM_SIZE ;; /* save in3 */
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| 180 | (p6) st8 [r31] = r34, -STACK_ITEM_SIZE ;; /* save in2 */
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| 181 | (p6) st8 [r31] = r33, -STACK_ITEM_SIZE ;; /* save in1 */
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| 182 | (p6) st8 [r31] = r32, -STACK_ITEM_SIZE ;; /* save in0 */
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| 183 | (p5) add r31 = -(7 * STACK_ITEM_SIZE), r31 ;;
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| 184 |
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| 185 | st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save old stack pointer */
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| 186 |
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| 187 | st8 [r31] = r29, -STACK_ITEM_SIZE ;; /* save predicate registers */
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| 188 |
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| 189 | st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save cr.iip */
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| 190 | st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save cr.ipsr */
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| 191 | st8 [r31] = r26, -STACK_ITEM_SIZE ;; /* save cr.iipa */
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| 192 | st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save cr.isr */
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| 193 | st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save cr.ifa */
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| 194 |
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| 195 | /* 5. RSE switch from interrupted context */
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| 196 | mov r24 = ar.rsc
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| 197 | mov r25 = ar.pfs
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| 198 | cover
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| 199 | mov r26 = cr.ifs
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| 200 |
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| 201 | st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save ar.rsc */
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| 202 | st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save ar.pfs */
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| 203 | st8 [r31] = r26, -STACK_ITEM_SIZE /* save ar.ifs */
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| 204 |
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| 205 | and r24 = ~(RSC_PL_MASK), r24 ;;
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| 206 | and r30 = ~(RSC_MODE_MASK), r24 ;;
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| 207 | mov ar.rsc = r30 ;; /* update RSE state */
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| 208 |
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| 209 | mov r27 = ar.rnat
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| 210 | mov r28 = ar.bspstore ;;
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| 211 |
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| 212 | /*
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| 213 | * Inspect BSPSTORE to figure out whether it is necessary to switch to
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| 214 | * kernel BSPSTORE.
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| 215 | */
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| 216 | (p1) shr.u r30 = r28, VRN_SHIFT ;;
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| 217 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
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| 218 |
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| 219 | /*
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| 220 | * If BSPSTORE needs to be switched, p1 is false and p2 is true.
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| 221 | */
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| 222 | (p1) mov r30 = r28
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| 223 | (p2) mov r30 = R_KSTACK_BSP ;;
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| 224 | (p2) mov ar.bspstore = r30 ;;
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| 225 |
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| 226 | mov r29 = ar.bsp
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| 227 |
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| 228 | st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save ar.rnat */
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| 229 | st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save new value written to ar.bspstore */
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| 230 | st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save ar.bspstore */
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| 231 | st8 [r31] = r29, -STACK_ITEM_SIZE /* save ar.bsp */
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| 232 |
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| 233 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
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| 234 |
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| 235 | /* steps 6 - 15 are done by heavyweight_handler_inner() */
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| 236 | mov R_RET = b0 /* save b0 belonging to interrupted context */
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| 237 | br.call.sptk.many b0 = heavyweight_handler_inner
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| 238 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
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| 239 |
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| 240 | /* 16. RSE switch to interrupted context */
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| 241 | cover /* allocate zero size frame (step 1 (from Intel Docs)) */
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| 242 |
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| 243 | add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_AR_BSP, r12 ;;
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| 244 |
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| 245 | ld8 r30 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bsp */
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| 246 | ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bspstore */
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| 247 | ld8 r28 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bspstore_new */
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| 248 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
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| 249 | shl r27 = r27, 16
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| 250 |
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| 251 | mov r24 = ar.rsc ;;
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| 252 | and r30 = ~3, r24 ;;
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| 253 | or r24 = r30 , r27 ;;
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| 254 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
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| 255 |
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| 256 | loadrs /* (step 3) */
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| 257 |
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| 258 | ld8 r27 = [r31], +STACK_ITEM_SIZE ;; /* load ar.rnat */
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| 259 | ld8 r26 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ifs */
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| 260 | ld8 r25 = [r31], +STACK_ITEM_SIZE ;; /* load ar.pfs */
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| 261 | ld8 r24 = [r31], +STACK_ITEM_SIZE ;; /* load ar.rsc */
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| 262 |
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| 263 | mov ar.bspstore = r29 ;; /* (step 4) */
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| 264 | mov ar.rnat = r27 /* (step 5) */
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| 265 |
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| 266 | mov ar.pfs = r25 /* (step 6) */
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| 267 | mov cr.ifs = r26
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| 268 |
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| 269 | mov ar.rsc = r24 /* (step 7) */
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| 270 |
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| 271 | /* 17. restore interruption state from memory stack */
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| 272 | ld8 r28 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ifa */
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| 273 | ld8 r27 = [r31], +STACK_ITEM_SIZE ;; /* load cr.isr */
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| 274 | ld8 r26 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iipa */
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| 275 | ld8 r25 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ipsr */
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| 276 | ld8 r24 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iip */
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| 277 |
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| 278 | mov cr.iip = r24;;
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| 279 | mov cr.iipa = r26
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| 280 | mov cr.isr = r27
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| 281 | mov cr.ifa = r28
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| 282 |
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| 283 | /* Set up FPU as in exception. */
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| 284 | mov r24 = psr
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| 285 | mov r26 = PSR_DFH_MASK
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| 286 | mov r27 = ~PSR_DFH_MASK ;;
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| 287 | and r25 = r25, r27
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| 288 | and r24 = r24, r26 ;;
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| 289 | or r25 = r25, r24 ;;
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| 290 | mov cr.ipsr = r25
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| 291 |
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| 292 | /* 18. restore predicate registers from memory stack */
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| 293 | ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load predicate registers */
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| 294 | mov pr = r29
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| 295 |
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| 296 | /* 19. return from interruption */
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| 297 | ld8 r12 = [r31] /* load stack pointer */
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| 298 | rfi ;;
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| 299 |
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| 300 | .global heavyweight_handler_inner
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| 301 | heavyweight_handler_inner:
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| 302 | /*
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| 303 | * From this point, the rest of the interrupted context
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| 304 | * will be preserved in stacked registers and backing store.
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| 305 | */
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| 306 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
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| 307 |
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| 308 | /* bank 0 is going to be shadowed, copy essential data from there */
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| 309 | mov loc1 = R_RET /* b0 belonging to interrupted context */
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| 310 | mov loc2 = R_HANDLER
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| 311 | mov out0 = R_OFFS
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| 312 |
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| 313 | add out1 = STACK_SCRATCH_AREA_SIZE, r12
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| 314 |
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| 315 | /* 6. switch to bank 1 and reenable PSR.ic */
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| 316 | ssm PSR_IC_MASK
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| 317 | bsw.1 ;;
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| 318 | srlz.d
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| 319 |
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| 320 | /* 7. preserve branch and application registers */
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| 321 | mov loc3 = ar.unat
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| 322 | mov loc4 = ar.lc
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| 323 | mov loc5 = ar.ec
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| 324 | mov loc6 = ar.ccv
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| 325 | mov loc7 = ar.csd
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| 326 | mov loc8 = ar.ssd
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| 327 |
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| 328 | mov loc9 = b0
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| 329 | mov loc10 = b1
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| 330 | mov loc11 = b2
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| 331 | mov loc12 = b3
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| 332 | mov loc13 = b4
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| 333 | mov loc14 = b5
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| 334 | mov loc15 = b6
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| 335 | mov loc16 = b7
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| 336 |
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| 337 | /* 8. preserve general and floating-point registers */
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| 338 | mov loc17 = r1
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| 339 | mov loc18 = r2
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| 340 | mov loc19 = r3
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| 341 | mov loc20 = r4
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| 342 | mov loc21 = r5
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| 343 | mov loc22 = r6
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| 344 | mov loc23 = r7
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| 345 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */
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| 346 | mov loc25 = r9
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| 347 | mov loc26 = r10
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| 348 | mov loc27 = r11
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| 349 | /* skip r12 (stack pointer) */
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| 350 | mov loc28 = r13
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| 351 | mov loc29 = r14
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| 352 | mov loc30 = r15
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| 353 | mov loc31 = r16
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| 354 | mov loc32 = r17
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| 355 | mov loc33 = r18
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| 356 | mov loc34 = r19
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| 357 | mov loc35 = r20
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| 358 | mov loc36 = r21
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| 359 | mov loc37 = r22
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| 360 | mov loc38 = r23
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| 361 | mov loc39 = r24
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| 362 | mov loc40 = r25
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| 363 | mov loc41 = r26
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| 364 | mov loc42 = r27
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| 365 | mov loc43 = r28
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| 366 | mov loc44 = r29
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| 367 | mov loc45 = r30
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| 368 | mov loc46 = r31
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| 369 |
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| 370 | add r24 = ISTATE_OFFSET_F8 + STACK_SCRATCH_AREA_SIZE, r12
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| 371 | add r25 = ISTATE_OFFSET_F9 + STACK_SCRATCH_AREA_SIZE, r12
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| 372 | add r26 = ISTATE_OFFSET_F2 + STACK_SCRATCH_AREA_SIZE, r12
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| 373 | add r27 = ISTATE_OFFSET_F3 + STACK_SCRATCH_AREA_SIZE, r12
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| 374 | add r28 = ISTATE_OFFSET_F4 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 375 | add r29 = ISTATE_OFFSET_F5 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 376 | add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 377 | add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
|
|---|
| 378 |
|
|---|
| 379 | stf.spill [r26] = f2, 8 * FLOAT_ITEM_SIZE
|
|---|
| 380 | stf.spill [r27] = f3, 8 * FLOAT_ITEM_SIZE
|
|---|
| 381 | stf.spill [r28] = f4, 8 * FLOAT_ITEM_SIZE
|
|---|
| 382 | stf.spill [r29] = f5, 8 * FLOAT_ITEM_SIZE
|
|---|
| 383 | stf.spill [r30] = f6, 8 * FLOAT_ITEM_SIZE
|
|---|
| 384 | stf.spill [r31] = f7, 8 * FLOAT_ITEM_SIZE ;;
|
|---|
| 385 |
|
|---|
| 386 | stf.spill [r24] = f8, 8 * FLOAT_ITEM_SIZE
|
|---|
| 387 | stf.spill [r25] = f9, 8 * FLOAT_ITEM_SIZE
|
|---|
| 388 | stf.spill [r26] = f10, 8 * FLOAT_ITEM_SIZE
|
|---|
| 389 | stf.spill [r27] = f11, 8 * FLOAT_ITEM_SIZE
|
|---|
| 390 | stf.spill [r28] = f12, 8 * FLOAT_ITEM_SIZE
|
|---|
| 391 | stf.spill [r29] = f13, 8 * FLOAT_ITEM_SIZE
|
|---|
| 392 | stf.spill [r30] = f14, 8 * FLOAT_ITEM_SIZE
|
|---|
| 393 | stf.spill [r31] = f15, 8 * FLOAT_ITEM_SIZE ;;
|
|---|
| 394 |
|
|---|
| 395 | stf.spill [r24] = f16, 8 * FLOAT_ITEM_SIZE
|
|---|
| 396 | stf.spill [r25] = f17, 8 * FLOAT_ITEM_SIZE
|
|---|
| 397 | stf.spill [r26] = f18, 8 * FLOAT_ITEM_SIZE
|
|---|
| 398 | stf.spill [r27] = f19, 8 * FLOAT_ITEM_SIZE
|
|---|
| 399 | stf.spill [r28] = f20, 8 * FLOAT_ITEM_SIZE
|
|---|
| 400 | stf.spill [r29] = f21, 8 * FLOAT_ITEM_SIZE
|
|---|
| 401 | stf.spill [r30] = f22, 8 * FLOAT_ITEM_SIZE
|
|---|
| 402 | stf.spill [r31] = f23, 8 * FLOAT_ITEM_SIZE ;;
|
|---|
| 403 |
|
|---|
| 404 | stf.spill [r24] = f24
|
|---|
| 405 | stf.spill [r25] = f25
|
|---|
| 406 | stf.spill [r26] = f26
|
|---|
| 407 | stf.spill [r27] = f27
|
|---|
| 408 | stf.spill [r28] = f28
|
|---|
| 409 | stf.spill [r29] = f29
|
|---|
| 410 | stf.spill [r30] = f30
|
|---|
| 411 | stf.spill [r31] = f31 ;;
|
|---|
| 412 |
|
|---|
| 413 | mov loc47 = ar.fpsr /* preserve floating point status register */
|
|---|
| 414 |
|
|---|
| 415 | /* 9. skipped (will not enable interrupts) */
|
|---|
| 416 | /*
|
|---|
| 417 | * ssm PSR_I_MASK
|
|---|
| 418 | * ;;
|
|---|
| 419 | * srlz.d
|
|---|
| 420 | */
|
|---|
| 421 |
|
|---|
| 422 | /* 10. call handler */
|
|---|
| 423 | movl r1 = __gp
|
|---|
| 424 |
|
|---|
| 425 | mov b1 = loc2
|
|---|
| 426 | br.call.sptk.many b0 = b1
|
|---|
| 427 |
|
|---|
| 428 | /* 11. return from handler */
|
|---|
| 429 | 0:
|
|---|
| 430 |
|
|---|
| 431 | /* 12. skipped (will not disable interrupts) */
|
|---|
| 432 | /*
|
|---|
| 433 | * rsm PSR_I_MASK
|
|---|
| 434 | * ;;
|
|---|
| 435 | * srlz.d
|
|---|
| 436 | */
|
|---|
| 437 |
|
|---|
| 438 | /* 13. restore general and floating-point registers */
|
|---|
| 439 | add r24 = ISTATE_OFFSET_F8 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 440 | add r25 = ISTATE_OFFSET_F9 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 441 | add r26 = ISTATE_OFFSET_F2 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 442 | add r27 = ISTATE_OFFSET_F3 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 443 | add r28 = ISTATE_OFFSET_F4 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 444 | add r29 = ISTATE_OFFSET_F5 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 445 | add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 446 | add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
|
|---|
| 447 |
|
|---|
| 448 | ldf.fill f2 = [r26], 8 * FLOAT_ITEM_SIZE
|
|---|
| 449 | ldf.fill f3 = [r27], 8 * FLOAT_ITEM_SIZE
|
|---|
| 450 | ldf.fill f4 = [r28], 8 * FLOAT_ITEM_SIZE
|
|---|
| 451 | ldf.fill f5 = [r29], 8 * FLOAT_ITEM_SIZE
|
|---|
| 452 | ldf.fill f6 = [r30], 8 * FLOAT_ITEM_SIZE
|
|---|
| 453 | ldf.fill f7 = [r31], 8 * FLOAT_ITEM_SIZE ;;
|
|---|
| 454 |
|
|---|
| 455 | ldf.fill f8 = [r24], 8 * FLOAT_ITEM_SIZE
|
|---|
| 456 | ldf.fill f9 = [r25], 8 * FLOAT_ITEM_SIZE
|
|---|
| 457 | ldf.fill f10 = [r26],8 * FLOAT_ITEM_SIZE
|
|---|
| 458 | ldf.fill f11 = [r27], 8 * FLOAT_ITEM_SIZE
|
|---|
| 459 | ldf.fill f12 = [r28], 8 * FLOAT_ITEM_SIZE
|
|---|
| 460 | ldf.fill f13 = [r29], 8 * FLOAT_ITEM_SIZE
|
|---|
| 461 | ldf.fill f14 = [r30], 8 * FLOAT_ITEM_SIZE
|
|---|
| 462 | ldf.fill f15 = [r31], 8 * FLOAT_ITEM_SIZE ;;
|
|---|
| 463 |
|
|---|
| 464 | ldf.fill f16 = [r24], 8 * FLOAT_ITEM_SIZE
|
|---|
| 465 | ldf.fill f17 = [r25], 8 * FLOAT_ITEM_SIZE
|
|---|
| 466 | ldf.fill f18 = [r26], 8 * FLOAT_ITEM_SIZE
|
|---|
| 467 | ldf.fill f19 = [r27], 8 * FLOAT_ITEM_SIZE
|
|---|
| 468 | ldf.fill f20 = [r28], 8 * FLOAT_ITEM_SIZE
|
|---|
| 469 | ldf.fill f21 = [r29], 8 * FLOAT_ITEM_SIZE
|
|---|
| 470 | ldf.fill f22 = [r30], 8 * FLOAT_ITEM_SIZE
|
|---|
| 471 | ldf.fill f23 = [r31], 8 * FLOAT_ITEM_SIZE ;;
|
|---|
| 472 |
|
|---|
| 473 | ldf.fill f24 = [r24]
|
|---|
| 474 | ldf.fill f25 = [r25]
|
|---|
| 475 | ldf.fill f26 = [r26]
|
|---|
| 476 | ldf.fill f27 = [r27]
|
|---|
| 477 | ldf.fill f28 = [r28]
|
|---|
| 478 | ldf.fill f29 = [r29]
|
|---|
| 479 | ldf.fill f30 = [r30]
|
|---|
| 480 | ldf.fill f31 = [r31] ;;
|
|---|
| 481 |
|
|---|
| 482 | mov r1 = loc17
|
|---|
| 483 | mov r2 = loc18
|
|---|
| 484 | mov r3 = loc19
|
|---|
| 485 | mov r4 = loc20
|
|---|
| 486 | mov r5 = loc21
|
|---|
| 487 | mov r6 = loc22
|
|---|
| 488 | mov r7 = loc23
|
|---|
| 489 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */
|
|---|
| 490 | mov r9 = loc25
|
|---|
| 491 | mov r10 = loc26
|
|---|
| 492 | mov r11 = loc27
|
|---|
| 493 | /* skip r12 (stack pointer) */
|
|---|
| 494 | mov r13 = loc28
|
|---|
| 495 | mov r14 = loc29
|
|---|
| 496 | mov r15 = loc30
|
|---|
| 497 | mov r16 = loc31
|
|---|
| 498 | mov r17 = loc32
|
|---|
| 499 | mov r18 = loc33
|
|---|
| 500 | mov r19 = loc34
|
|---|
| 501 | mov r20 = loc35
|
|---|
| 502 | mov r21 = loc36
|
|---|
| 503 | mov r22 = loc37
|
|---|
| 504 | mov r23 = loc38
|
|---|
| 505 | mov r24 = loc39
|
|---|
| 506 | mov r25 = loc40
|
|---|
| 507 | mov r26 = loc41
|
|---|
| 508 | mov r27 = loc42
|
|---|
| 509 | mov r28 = loc43
|
|---|
| 510 | mov r29 = loc44
|
|---|
| 511 | mov r30 = loc45
|
|---|
| 512 | mov r31 = loc46
|
|---|
| 513 |
|
|---|
| 514 | mov ar.fpsr = loc47 /* restore floating point status register */
|
|---|
| 515 |
|
|---|
| 516 | /* 14. restore branch and application registers */
|
|---|
| 517 | mov ar.unat = loc3
|
|---|
| 518 | mov ar.lc = loc4
|
|---|
| 519 | mov ar.ec = loc5
|
|---|
| 520 | mov ar.ccv = loc6
|
|---|
| 521 | mov ar.csd = loc7
|
|---|
| 522 | mov ar.ssd = loc8
|
|---|
| 523 |
|
|---|
| 524 | mov b0 = loc9
|
|---|
| 525 | mov b1 = loc10
|
|---|
| 526 | mov b2 = loc11
|
|---|
| 527 | mov b3 = loc12
|
|---|
| 528 | mov b4 = loc13
|
|---|
| 529 | mov b5 = loc14
|
|---|
| 530 | mov b6 = loc15
|
|---|
| 531 | mov b7 = loc16
|
|---|
| 532 |
|
|---|
| 533 | /* 15. disable PSR.ic and switch to bank 0 */
|
|---|
| 534 | rsm PSR_IC_MASK
|
|---|
| 535 | bsw.0 ;;
|
|---|
| 536 | srlz.d
|
|---|
| 537 |
|
|---|
| 538 | mov R_RET = loc1
|
|---|
| 539 | mov ar.pfs = loc0
|
|---|
| 540 | br.ret.sptk.many b0
|
|---|
| 541 |
|
|---|
| 542 | .global ivt
|
|---|
| 543 | .align 32768
|
|---|
| 544 | ivt:
|
|---|
| 545 | HEAVYWEIGHT_HANDLER 0x0000
|
|---|
| 546 | HEAVYWEIGHT_HANDLER 0x0400
|
|---|
| 547 | HEAVYWEIGHT_HANDLER 0x0800
|
|---|
| 548 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
|
|---|
| 549 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
|
|---|
| 550 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
|
|---|
| 551 | HEAVYWEIGHT_HANDLER 0x1800
|
|---|
| 552 | HEAVYWEIGHT_HANDLER 0x1c00
|
|---|
| 553 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
|
|---|
| 554 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
|
|---|
| 555 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
|
|---|
| 556 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
|
|---|
| 557 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
|
|---|
| 558 | HEAVYWEIGHT_HANDLER 0x3400
|
|---|
| 559 | HEAVYWEIGHT_HANDLER 0x3800
|
|---|
| 560 | HEAVYWEIGHT_HANDLER 0x3c00
|
|---|
| 561 | HEAVYWEIGHT_HANDLER 0x4000
|
|---|
| 562 | HEAVYWEIGHT_HANDLER 0x4400
|
|---|
| 563 | HEAVYWEIGHT_HANDLER 0x4800
|
|---|
| 564 | HEAVYWEIGHT_HANDLER 0x4c00
|
|---|
| 565 |
|
|---|
| 566 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present
|
|---|
| 567 | HEAVYWEIGHT_HANDLER 0x5100
|
|---|
| 568 | HEAVYWEIGHT_HANDLER 0x5200
|
|---|
| 569 | HEAVYWEIGHT_HANDLER 0x5300 data_access_rights_fault
|
|---|
| 570 | HEAVYWEIGHT_HANDLER 0x5400 general_exception
|
|---|
| 571 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
|
|---|
| 572 | HEAVYWEIGHT_HANDLER 0x5600
|
|---|
| 573 | SPECULATION_VECTOR_HANDLER 0x5700
|
|---|
| 574 | HEAVYWEIGHT_HANDLER 0x5800
|
|---|
| 575 | HEAVYWEIGHT_HANDLER 0x5900
|
|---|
| 576 | HEAVYWEIGHT_HANDLER 0x5a00
|
|---|
| 577 | HEAVYWEIGHT_HANDLER 0x5b00
|
|---|
| 578 | HEAVYWEIGHT_HANDLER 0x5c00
|
|---|
| 579 | HEAVYWEIGHT_HANDLER 0x5d00
|
|---|
| 580 | HEAVYWEIGHT_HANDLER 0x5e00
|
|---|
| 581 | HEAVYWEIGHT_HANDLER 0x5f00
|
|---|
| 582 |
|
|---|
| 583 | HEAVYWEIGHT_HANDLER 0x6000
|
|---|
| 584 | HEAVYWEIGHT_HANDLER 0x6100
|
|---|
| 585 | HEAVYWEIGHT_HANDLER 0x6200
|
|---|
| 586 | HEAVYWEIGHT_HANDLER 0x6300
|
|---|
| 587 | HEAVYWEIGHT_HANDLER 0x6400
|
|---|
| 588 | HEAVYWEIGHT_HANDLER 0x6500
|
|---|
| 589 | HEAVYWEIGHT_HANDLER 0x6600
|
|---|
| 590 | HEAVYWEIGHT_HANDLER 0x6700
|
|---|
| 591 | HEAVYWEIGHT_HANDLER 0x6800
|
|---|
| 592 | HEAVYWEIGHT_HANDLER 0x6900
|
|---|
| 593 | HEAVYWEIGHT_HANDLER 0x6a00
|
|---|
| 594 | HEAVYWEIGHT_HANDLER 0x6b00
|
|---|
| 595 | HEAVYWEIGHT_HANDLER 0x6c00
|
|---|
| 596 | HEAVYWEIGHT_HANDLER 0x6d00
|
|---|
| 597 | HEAVYWEIGHT_HANDLER 0x6e00
|
|---|
| 598 | HEAVYWEIGHT_HANDLER 0x6f00
|
|---|
| 599 |
|
|---|
| 600 | HEAVYWEIGHT_HANDLER 0x7000
|
|---|
| 601 | HEAVYWEIGHT_HANDLER 0x7100
|
|---|
| 602 | HEAVYWEIGHT_HANDLER 0x7200
|
|---|
| 603 | HEAVYWEIGHT_HANDLER 0x7300
|
|---|
| 604 | HEAVYWEIGHT_HANDLER 0x7400
|
|---|
| 605 | HEAVYWEIGHT_HANDLER 0x7500
|
|---|
| 606 | HEAVYWEIGHT_HANDLER 0x7600
|
|---|
| 607 | HEAVYWEIGHT_HANDLER 0x7700
|
|---|
| 608 | HEAVYWEIGHT_HANDLER 0x7800
|
|---|
| 609 | HEAVYWEIGHT_HANDLER 0x7900
|
|---|
| 610 | HEAVYWEIGHT_HANDLER 0x7a00
|
|---|
| 611 | HEAVYWEIGHT_HANDLER 0x7b00
|
|---|
| 612 | HEAVYWEIGHT_HANDLER 0x7c00
|
|---|
| 613 | HEAVYWEIGHT_HANDLER 0x7d00
|
|---|
| 614 | HEAVYWEIGHT_HANDLER 0x7e00
|
|---|
| 615 | HEAVYWEIGHT_HANDLER 0x7f00
|
|---|
