source: mainline/kernel/arch/ia64/src/ia64.c@ f7aaffe0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f7aaffe0 was 3bacee1, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Make ccheck-fix again and commit more good files.

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File size: 7.4 KB
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[2a0047fc]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[2a0047fc]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[244f284]35#include <arch.h>
[36df4109]36#include <arch/arch.h>
[d99c1d2]37#include <typedefs.h>
[d8db519]38#include <errno.h>
[3a2f8aa]39#include <interrupt.h>
[9928240]40#include <arch/interrupt.h>
[4872160]41#include <macros.h>
[76d0981d]42#include <stdbool.h>
[d8db519]43#include <str.h>
[b994a60]44#include <userspace.h>
[a8c48241]45#include <console/console.h>
[e1be3b6]46#include <syscall/syscall.h>
[d8db519]47#include <sysinfo/sysinfo.h>
48#include <arch/drivers/it.h>
49#include <arch/drivers/kbd.h>
[22f0561]50#include <arch/legacyio.h>
[f245145]51#include <genarch/drivers/ega/ega.h>
[411b6a6]52#include <genarch/drivers/i8042/i8042.h>
[4c84368e]53#include <genarch/drivers/ns16550/ns16550.h>
[d8db519]54#include <genarch/drivers/legacy/ia32/io.h>
55#include <genarch/kbrd/kbrd.h>
56#include <genarch/srln/srln.h>
[22f0561]57#include <mm/page.h>
[d4673296]58#include <mm/km.h>
[22f0561]59
60#ifdef MACHINE_ski
61#include <arch/drivers/ski.h>
62#endif
[59e4864]63
[36df4109]64static void ia64_pre_mm_init(void);
65static void ia64_post_mm_init(void);
66static void ia64_post_smp_init(void);
67
68arch_ops_t ia64_ops = {
69 .pre_mm_init = ia64_pre_mm_init,
70 .post_mm_init = ia64_post_mm_init,
71 .post_smp_init = ia64_post_smp_init,
72};
73
74arch_ops_t *arch_ops = &ia64_ops;
75
[666773c]76/* NS16550 as a COM 1 */
[449d4ecc]77#define NS16550_IRQ (4 + LEGACY_INTERRUPT_BASE)
[743ffa6e]78
79bootinfo_t *bootinfo;
[586262f]80
[666773c]81static uint64_t iosapic_base = 0xfec00000;
[22f0561]82uintptr_t legacyio_virt_base = 0;
[323a5aaf]83
[06f96234]84/** Performs ia64-specific initialization before main_bsp() is called. */
[36df4109]85void ia64_pre_main(void)
[6ecc8bce]86{
[32817cc]87 init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS,
88 CONFIG_INIT_TASKS);
[4872160]89 size_t i;
[32817cc]90
[6c441cf8]91 for (i = 0; i < init.cnt; i++) {
[32817cc]92 init.tasks[i].paddr =
93 (uintptr_t) bootinfo->taskmap.tasks[i].addr;
[6c441cf8]94 init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
[f4b1535]95 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
96 bootinfo->taskmap.tasks[i].name);
[743ffa6e]97 }
[6ecc8bce]98}
99
[36df4109]100void ia64_pre_mm_init(void)
[244f284]101{
[9928240]102 if (config.cpu_active == 1)
103 exception_init();
[244f284]104}
105
[323a5aaf]106static void iosapic_init(void)
107{
[adec5b45]108 uintptr_t IOSAPIC = km_map(iosapic_base, PAGE_SIZE,
109 PAGE_WRITE | PAGE_NOT_CACHEABLE);
[323a5aaf]110 int i;
[a35b458]111
[2b70a6e]112 int myid, myeid;
[a35b458]113
[666773c]114 myid = ia64_get_cpu_id();
115 myeid = ia64_get_cpu_eid();
[50b3d30]116
[1b20da0]117 for (i = 0; i < 16; i++) {
[666773c]118 if (i == 2)
119 continue; /* Disable Cascade interrupt */
120 ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i;
[323a5aaf]121 srlz_d();
[666773c]122 ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i;
[323a5aaf]123 srlz_d();
[666773c]124 ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1;
[323a5aaf]125 srlz_d();
[666773c]126 ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) |
127 myeid << (48 - 32);
[323a5aaf]128 srlz_d();
129 }
130
131}
132
[36df4109]133void ia64_post_mm_init(void)
[244f284]134{
[666773c]135 if (config.cpu_active == 1) {
[22f0561]136 /* Map the page with legacy I/O. */
[adec5b45]137 legacyio_virt_base = km_map(LEGACYIO_PHYS_BASE, LEGACYIO_SIZE,
138 PAGE_WRITE | PAGE_NOT_CACHEABLE);
[22f0561]139
[323a5aaf]140 iosapic_init();
[59e4864]141 irq_init(INR_COUNT, INR_COUNT);
142 }
[1b20da0]143 it_init();
[244f284]144}
[7453929]145
[36df4109]146void ia64_post_smp_init(void)
[7453929]147{
[eff1f033]148 static const char *platform;
149
150 /* Set platform name. */
151#ifdef MACHINE_ski
[3714e79]152 platform = "ski";
[eff1f033]153#endif
154#ifdef MACHINE_i460GX
[26f407e9]155 platform = "pc";
[eff1f033]156#endif
157 sysinfo_set_item_data("platform", NULL, (void *) platform,
158 str_size(platform));
159
[c2417bc]160#ifdef MACHINE_ski
161 ski_instance_t *ski_instance = skiin_init();
162 if (ski_instance) {
163 srln_instance_t *srln_instance = srln_init();
164 if (srln_instance) {
165 indev_t *sink = stdin_wire();
166 indev_t *srln = srln_wire(srln_instance, sink);
167 skiin_wire(ski_instance, srln);
168 }
169 }
[a35b458]170
[a71c158]171 outdev_t *skidev = skiout_init();
172 if (skidev)
173 stdout_wire(skidev);
[1462d35]174#endif
[a35b458]175
[2270bef]176#ifdef CONFIG_EGA
[a71c158]177 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
178 if (egadev)
179 stdout_wire(egadev);
[2270bef]180#endif
[a35b458]181
[59e4864]182#ifdef CONFIG_NS16550
[3bacee1]183 ns16550_instance_t *ns16550_instance =
184 ns16550_init(NS16550_BASE, 0, NS16550_IRQ, NULL, NULL,
[21b6307]185 NULL);
[c2417bc]186 if (ns16550_instance) {
187 srln_instance_t *srln_instance = srln_init();
188 if (srln_instance) {
189 indev_t *sink = stdin_wire();
190 indev_t *srln = srln_wire(srln_instance, sink);
191 ns16550_wire(ns16550_instance, srln);
192 }
193 }
[a35b458]194
[449d4ecc]195 sysinfo_set_item_val("kbd", NULL, true);
196 sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ);
[4c7257b]197 sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
[ff685c9]198 sysinfo_set_item_val("kbd.address.physical", NULL,
199 (uintptr_t) NS16550_BASE);
[449d4ecc]200#endif
[a35b458]201
[449d4ecc]202#ifdef CONFIG_I8042
[88dfee7]203 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE,
204 IRQ_KBD);
[c2417bc]205 if (i8042_instance) {
206 kbrd_instance_t *kbrd_instance = kbrd_init();
207 if (kbrd_instance) {
208 indev_t *sink = stdin_wire();
209 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
210 i8042_wire(i8042_instance, kbrd);
211 }
212 }
[59e4864]213#endif
[a35b458]214
[46321fb]215 sysinfo_set_item_val("ia64_iospace", NULL, true);
216 sysinfo_set_item_val("ia64_iospace.address", NULL, true);
[22f0561]217 sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, LEGACYIO_USER_BASE);
[7453929]218}
[b994a60]219
[59e4864]220
[b994a60]221/** Enter userspace and never return. */
[0f250f9]222void userspace(uspace_arg_t *kernel_uarg)
[b994a60]223{
224 psr_t psr;
225 rsc_t rsc;
226
227 psr.value = psr_read();
228 psr.cpl = PL_USER;
[666773c]229 psr.i = true; /* start with interrupts enabled */
[b994a60]230 psr.ic = true;
[666773c]231 psr.ri = 0; /* start with instruction #0 */
232 psr.bn = 1; /* start in bank 0 */
[b994a60]233
[e7b7be3f]234 asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
[b994a60]235 rsc.loadrs = 0;
236 rsc.be = false;
237 rsc.pl = PL_USER;
[666773c]238 rsc.mode = 3; /* eager mode */
[b994a60]239
[2f23341]240 /*
241 * Switch to userspace.
242 *
243 * When calculating stack addresses, mind the stack split between the
[2902e1bb]244 * memory stack and the RSE stack. Each occuppies
245 * uspace_stack_size / 2 bytes.
[2f23341]246 */
[7f1c620]247 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
[2902e1bb]248 ((uintptr_t) kernel_uarg->uspace_stack) +
249 kernel_uarg->uspace_stack_size / 2 -
[666773c]250 ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
[2902e1bb]251 ((uintptr_t) kernel_uarg->uspace_stack) +
252 kernel_uarg->uspace_stack_size / 2,
[666773c]253 (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
[a35b458]254
[3bacee1]255 while (true)
256 ;
[b994a60]257}
[e1be3b6]258
[f74bbaf]259void arch_reboot(void)
260{
[013c4d6]261 pio_write_8((ioport8_t *)0x64, 0xfe);
[3bacee1]262 while (true)
263 ;
[f74bbaf]264}
265
[6da1013f]266/** Construct function pointer
267 *
268 * @param fptr function pointer structure
269 * @param addr function address
270 * @param caller calling function address
271 *
272 * @return address of the function pointer
273 *
274 */
275void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
276{
[96b02eb9]277 fptr->fnc = (sysarg_t) addr;
278 fptr->gp = ((sysarg_t *) caller)[1];
[a35b458]279
[6da1013f]280 return (void *) fptr;
281}
282
[3a2f8aa]283void irq_initialize_arch(irq_t *irq)
284{
285 (void) irq;
286}
287
[06e1e95]288/** @}
[b45c443]289 */
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