[154049e] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Jakub Jermar
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[154049e] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[84afc7b] | 29 | /** @addtogroup ia64
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[154049e] | 35 | /** Interval Timer driver. */
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[da1bafb] | 36 |
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[154049e] | 37 | #include <arch/drivers/it.h>
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| 38 | #include <arch/interrupt.h>
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| 39 | #include <arch/register.h>
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| 40 | #include <arch/asm.h>
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| 41 | #include <arch/barrier.h>
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| 42 | #include <time/clock.h>
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[de57e060] | 43 | #include <ddi/irq.h>
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| 44 | #include <ddi/device.h>
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[bd571f44] | 45 | #include <arch.h>
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[154049e] | 46 |
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[da1bafb] | 47 | #define IT_SERVICE_CLOCKS 64
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[bd571f44] | 48 |
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[da1bafb] | 49 | #define FREQ_NUMERATOR_SHIFT 32
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| 50 | #define FREQ_NUMERATOR_MASK 0xffffffff00000000ULL
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[1025d28] | 51 |
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[da1bafb] | 52 | #define FREQ_DENOMINATOR_SHIFT 0
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| 53 | #define FREQ_DENOMINATOR_MASK 0xffffffffULL
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[1025d28] | 54 |
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| 55 | uint64_t it_delta;
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| 56 |
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[de57e060] | 57 | static irq_t it_irq;
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| 58 |
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[c9b550b] | 59 | static irq_ownership_t it_claim(irq_t *);
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| 60 | static void it_interrupt(irq_t *);
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[de57e060] | 61 |
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[154049e] | 62 | /** Initialize Interval Timer. */
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| 63 | void it_init(void)
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| 64 | {
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[666773c] | 65 | if (config.cpu_active == 1) {
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[59e4864] | 66 | irq_initialize(&it_irq);
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| 67 | it_irq.inr = INTERRUPT_TIMER;
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| 68 | it_irq.devno = device_assign_devno();
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| 69 | it_irq.claim = it_claim;
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| 70 | it_irq.handler = it_interrupt;
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| 71 | irq_register(&it_irq);
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[1025d28] | 72 |
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| 73 | uint64_t base_freq;
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[666773c] | 74 | base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >>
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| 75 | FREQ_NUMERATOR_SHIFT;
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[1025d28] | 76 | base_freq *= bootinfo->sys_freq;
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[666773c] | 77 | base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >>
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| 78 | FREQ_DENOMINATOR_SHIFT;
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[1025d28] | 79 |
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[666773c] | 80 | it_delta = base_freq / HZ;
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[59e4864] | 81 | }
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| 82 |
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[da1bafb] | 83 | /* Initialize Interval Timer external interrupt vector */
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| 84 | cr_itv_t itv;
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| 85 |
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[154049e] | 86 | itv.value = itv_read();
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| 87 | itv.vector = INTERRUPT_TIMER;
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| 88 | itv.m = 0;
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| 89 | itv_write(itv.value);
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[da1bafb] | 90 |
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| 91 | /* Set Interval Timer Counter to zero */
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[154049e] | 92 | itc_write(0);
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| 93 |
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[da1bafb] | 94 | /* Generate first Interval Timer interrupt in IT_DELTA ticks */
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[154049e] | 95 | itm_write(IT_DELTA);
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[da1bafb] | 96 |
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| 97 | /* Propagate changes */
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[154049e] | 98 | srlz_d();
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| 99 | }
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| 100 |
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[de57e060] | 101 | /** Always claim ownership for this IRQ.
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| 102 | *
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| 103 | * Other devices are responsible to avoid using INR 0.
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| 104 | *
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| 105 | * @return Always IRQ_ACCEPT.
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[da1bafb] | 106 | *
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[de57e060] | 107 | */
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[c9b550b] | 108 | irq_ownership_t it_claim(irq_t *irq)
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[de57e060] | 109 | {
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| 110 | return IRQ_ACCEPT;
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| 111 | }
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[bd571f44] | 112 |
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[154049e] | 113 | /** Process Interval Timer interrupt. */
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[6cd9aa6] | 114 | void it_interrupt(irq_t *irq)
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[154049e] | 115 | {
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| 116 | eoi_write(EOI);
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[bd571f44] | 117 |
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[da1bafb] | 118 | int64_t itm = itm_read();
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[bd571f44] | 119 |
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[da1bafb] | 120 | while (true) {
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| 121 | int64_t itc = itc_read();
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| 122 | itc += IT_SERVICE_CLOCKS;
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| 123 |
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| 124 | itm += IT_DELTA;
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| 125 | if (itm - itc < 0)
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[bd571f44] | 126 | CPU->missed_clock_ticks++;
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[9a5b556] | 127 | else
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| 128 | break;
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[bd571f44] | 129 | }
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| 130 |
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[da1bafb] | 131 | itm_write(itm);
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| 132 | srlz_d(); /* Propagate changes */
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| 133 |
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[f619ec11] | 134 | /*
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| 135 | * We are holding a lock which prevents preemption.
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| 136 | * Release the lock, call clock() and reacquire the lock again.
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| 137 | */
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[da1bafb] | 138 | irq_spinlock_unlock(&irq->lock, false);
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[154049e] | 139 | clock();
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[da1bafb] | 140 | irq_spinlock_lock(&irq->lock, false);
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[154049e] | 141 | }
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[b45c443] | 142 |
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[9a5b556] | 143 | /** @}
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[b45c443] | 144 | */
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