source: mainline/kernel/arch/ia64/include/atomic.h@ 2f57690

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2f57690 was 8b4d6cb, checked in by Jakub Jermar <jakub@…>, 17 years ago

More of ia64 cleanup.

  • Property mode set to 100644
File size: 2.5 KB
RevLine 
[b0bf501]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[b0bf501]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_ia64_ATOMIC_H_
36#define KERN_ia64_ATOMIC_H_
[b0bf501]37
[10c071e]38/** Atomic addition.
39 *
[8b4d6cb]40 * @param val Atomic value.
41 * @param imm Value to add.
[10c071e]42 *
[8b4d6cb]43 * @return Value before addition.
[10c071e]44 */
[23684b7]45static inline long atomic_add(atomic_t *val, int imm)
[59e07c91]46{
[23684b7]47 long v;
[59e07c91]48
[8b4d6cb]49 asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v),
50 "+m" (val->count) : "i" (imm));
[73a4bab]51
[59e07c91]52 return v;
[b0bf501]53}
54
[59e4864]55
56static inline uint64_t test_and_set(atomic_t *val) {
57 uint64_t v;
58
59 asm volatile (
[8b4d6cb]60 "movl %0 = 0x01;;\n"
61 "xchg8 %0 = %1, %0;;\n"
62 : "=r" (v), "+m" (val->count)
[59e4864]63 );
64
65 return v;
66}
67
68
[8b4d6cb]69static inline void atomic_inc(atomic_t *val)
70{
71 atomic_add(val, 1);
72}
73
74static inline void atomic_dec(atomic_t *val)
75{
76 atomic_add(val, -1);
77}
[73a4bab]78
[8b4d6cb]79static inline long atomic_preinc(atomic_t *val)
80{
81 return atomic_add(val, 1) + 1;
82}
[73a4bab]83
[8b4d6cb]84static inline long atomic_predec(atomic_t *val)
85{
86 return atomic_add(val, -1) - 1;
87}
88
89static inline long atomic_postinc(atomic_t *val)
90{
91 return atomic_add(val, 1);
92}
93
94static inline long atomic_postdec(atomic_t *val)
95{
96 return atomic_add(val, -1);
97}
[59e07c91]98
[b0bf501]99#endif
[b45c443]100
[06e1e95]101/** @}
[b45c443]102 */
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