source: mainline/kernel/arch/ia32/src/interrupt.c@ 935e28c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 935e28c was 1066041, checked in by Adam Hraska <adam.hraska+hos@…>, 13 years ago

preemption_disable: Turned functions into macros. Moved THREAD, AS, TASK, CPU into thread.h, as.h, task.h, cpu.h to fix the include hell that ensued.

  • Property mode set to 100644
File size: 7.1 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[b6529ae]29/** @addtogroup ia32interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch/interrupt.h>
[204674e]36#include <syscall/syscall.h>
[f761f1eb]37#include <print.h>
[02a99d2]38#include <debug.h>
[f761f1eb]39#include <panic.h>
[80d31883]40#include <arch/drivers/i8259.h>
[f761f1eb]41#include <func.h>
42#include <cpu.h>
43#include <arch/asm.h>
[169587a]44#include <mm/tlb.h>
[20d50a1]45#include <mm/as.h>
[cb4b61d]46#include <arch.h>
[1084a784]47#include <proc/thread.h>
[2382d09]48#include <proc/task.h>
49#include <synch/spinlock.h>
50#include <arch/ddi/ddi.h>
[5626277]51#include <ipc/sysipc.h>
52#include <interrupt.h>
[cea12e9]53#include <ddi/irq.h>
[e2b762ec]54#include <symtab.h>
[203deeb8]55#include <stacktrace.h>
[2ee1ccc]56#include <smp/smp_call.h>
[1066041]57#include <proc/task.h>
[e2b762ec]58
[f761f1eb]59/*
60 * Interrupt and exception dispatching.
61 */
62
[7f1c620]63void (* disable_irqs_function)(uint16_t irqmask) = NULL;
64void (* enable_irqs_function)(uint16_t irqmask) = NULL;
[f761f1eb]65void (* eoi_function)(void) = NULL;
[acc7ce4]66const char *irqs_info = NULL;
[f761f1eb]67
[22a28a69]68void istate_decode(istate_t *istate)
[97b64c9]69{
[f36787d7]70 printf("cs =%0#10" PRIx32 "\teip=%0#10" PRIx32 "\t"
71 "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n",
72 istate->cs, istate->eip, istate->eflags, istate->error_word);
[7e752b2]73
[f36787d7]74 printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t"
75 "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n",
[0d1e976]76 istate->ds, istate->es, istate->fs, istate->gs);
[7e752b2]77
[c9eb31c2]78 if (istate_from_uspace(istate))
[f36787d7]79 printf("ss =%0#10" PRIx32 "\n", istate->ss);
[7e752b2]80
[f36787d7]81 printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t"
82 "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n",
[0d1e976]83 istate->eax, istate->ebx, istate->ecx, istate->edx);
[7e752b2]84
[f36787d7]85 printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t"
86 "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIx32 "\n",
87 istate->esi, istate->edi, istate->ebp,
88 istate_from_uspace(istate) ? istate->esp :
89 (uintptr_t) &istate->esp);
[97b64c9]90}
[ab08b42]91
[cea12e9]92static void trap_virtual_eoi(void)
93{
94 if (eoi_function)
95 eoi_function();
96 else
[f651e80]97 panic("No eoi_function.");
[cea12e9]98
99}
100
[214ec25c]101static void null_interrupt(unsigned int n, istate_t *istate)
[f761f1eb]102{
[214ec25c]103 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
[62baed17]104 panic_badtrap(istate, n, "Unserviced interrupt: %u.", n);
[f761f1eb]105}
106
[214ec25c]107static void de_fault(unsigned int n, istate_t *istate)
[4491338]108{
109 fault_if_from_uspace(istate, "Divide error.");
[62baed17]110 panic_badtrap(istate, n, "Divide error.");
[4491338]111}
112
[2382d09]113/** General Protection Fault. */
[214ec25c]114static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[f761f1eb]115{
[2382d09]116 if (TASK) {
[da1bafb]117 irq_spinlock_lock(&TASK->lock, false);
118 size_t ver = TASK->arch.iomapver;
119 irq_spinlock_unlock(&TASK->lock, false);
[2382d09]120
121 if (CPU->arch.iomapver_copy != ver) {
122 /*
123 * This fault can be caused by an early access
124 * to I/O port because of an out-dated
125 * I/O Permission bitmap installed on CPU.
126 * Install the fresh copy and restart
127 * the instruction.
128 */
129 io_perm_bitmap_install();
130 return;
131 }
[f651e80]132 fault_if_from_uspace(istate, "General protection fault.");
[2382d09]133 }
[62baed17]134 panic_badtrap(istate, n, "General protection fault.");
[f761f1eb]135}
136
[214ec25c]137static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[6de2480e]138{
[f651e80]139 fault_if_from_uspace(istate, "Stack fault.");
[62baed17]140 panic_badtrap(istate, n, "Stack fault.");
[6de2480e]141}
142
[214ec25c]143static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate)
[3b05862f]144{
[7f1c620]145 uint32_t mxcsr;
[da1bafb]146 asm volatile (
[add04f7]147 "stmxcsr %[mxcsr]\n"
148 : [mxcsr] "=m" (mxcsr)
[3b05862f]149 );
[da1bafb]150
[7e752b2]151 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
152 mxcsr);
153 panic_badtrap(istate, n, "SIMD FP exception");
[3b05862f]154}
155
[214ec25c]156static void nm_fault(unsigned int n __attribute__((unused)),
[da1bafb]157 istate_t *istate __attribute__((unused)))
[6a27d63]158{
[da1bafb]159#ifdef CONFIG_FPU_LAZY
[b49f4ae]160 scheduler_fpu_lazy_request();
161#else
[f651e80]162 fault_if_from_uspace(istate, "FPU fault.");
[62baed17]163 panic_badtrap(istate, n, "FPU fault.");
[b49f4ae]164#endif
[6a27d63]165}
166
[cea12e9]167#ifdef CONFIG_SMP
[214ec25c]168static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)),
[da1bafb]169 istate_t *istate __attribute__((unused)))
[f761f1eb]170{
[cea12e9]171 trap_virtual_eoi();
172 tlb_shootdown_ipi_recv();
[f761f1eb]173}
[2ee1ccc]174
175static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
176{
177 trap_virtual_eoi();
178 smp_call_ipi_recv();
179}
[cea12e9]180#endif
[f761f1eb]181
[cea12e9]182/** Handler of IRQ exceptions */
[214ec25c]183static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused)))
[169587a]184{
[cea12e9]185 ASSERT(n >= IVT_IRQBASE);
186
[214ec25c]187 unsigned int inum = n - IVT_IRQBASE;
[7bcfbbc]188 bool ack = false;
[cea12e9]189 ASSERT(inum < IRQ_COUNT);
190 ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
[7bcfbbc]191
[cea12e9]192 irq_t *irq = irq_dispatch_and_lock(inum);
193 if (irq) {
194 /*
195 * The IRQ handler was found.
196 */
[da1bafb]197
[7bcfbbc]198 if (irq->preack) {
199 /* Send EOI before processing the interrupt */
200 trap_virtual_eoi();
201 ack = true;
202 }
[6cd9aa6]203 irq->handler(irq);
[da1bafb]204 irq_spinlock_unlock(&irq->lock, false);
[cea12e9]205 } else {
206 /*
207 * Spurious interrupt.
208 */
209#ifdef CONFIG_DEBUG
[214ec25c]210 printf("cpu%u: spurious interrupt (inum=%u)\n", CPU->id, inum);
[cea12e9]211#endif
212 }
[7bcfbbc]213
214 if (!ack)
215 trap_virtual_eoi();
[cea12e9]216}
217
218void interrupt_init(void)
219{
[b3b7e14a]220 unsigned int i;
[cea12e9]221
222 for (i = 0; i < IVT_ITEMS; i++)
[b3b7e14a]223 exc_register(i, "null", false, (iroutine_t) null_interrupt);
[cea12e9]224
225 for (i = 0; i < IRQ_COUNT; i++) {
226 if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
[b3b7e14a]227 exc_register(IVT_IRQBASE + i, "irq", true,
228 (iroutine_t) irq_interrupt);
[cea12e9]229 }
230
[b3b7e14a]231 exc_register(0, "de_fault", true, (iroutine_t) de_fault);
232 exc_register(7, "nm_fault", true, (iroutine_t) nm_fault);
233 exc_register(12, "ss_fault", true, (iroutine_t) ss_fault);
234 exc_register(13, "gp_fault", true, (iroutine_t) gp_fault);
235 exc_register(19, "simd_fp", true, (iroutine_t) simd_fp_exception);
[cea12e9]236
237#ifdef CONFIG_SMP
[b3b7e14a]238 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
239 (iroutine_t) tlb_shootdown_ipi);
[2ee1ccc]240 exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
241 (iroutine_t) arch_smp_call_ipi_recv);
[cea12e9]242#endif
[169587a]243}
244
[7f1c620]245void trap_virtual_enable_irqs(uint16_t irqmask)
[f761f1eb]246{
247 if (enable_irqs_function)
248 enable_irqs_function(irqmask);
249 else
[f651e80]250 panic("No enable_irqs_function.");
[f761f1eb]251}
252
[7f1c620]253void trap_virtual_disable_irqs(uint16_t irqmask)
[f761f1eb]254{
255 if (disable_irqs_function)
256 disable_irqs_function(irqmask);
257 else
[f651e80]258 panic("No disable_irqs_function.");
[f761f1eb]259}
260
[3222efd]261/** @}
[b45c443]262 */
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