source: mainline/kernel/arch/ia32/src/ia32.c@ 26678e5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 26678e5 was 26678e5, checked in by Jakub Jermar <jakub@…>, 19 years ago

Make SMP related parts of main.c more generic.
Move initialization of local APIC to architecture specific code.
Add arch_post_cpu_init() to support the above.

  • Property mode set to 100644
File size: 3.8 KB
RevLine 
[f761f1eb]1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch.h>
36
37#include <arch/types.h>
38#include <typedefs.h>
39
40#include <arch/pm.h>
41
[018f95a]42#include <arch/drivers/ega.h>
[80d31883]43#include <arch/drivers/vesa.h>
[287920f]44#include <genarch/kbd/i8042.h>
[80d31883]45#include <arch/drivers/i8254.h>
46#include <arch/drivers/i8259.h>
[f761f1eb]47
48#include <arch/context.h>
49
50#include <config.h>
51
52#include <arch/interrupt.h>
[ad36bd6]53#include <arch/asm.h>
[e16e036a]54#include <genarch/acpi/acpi.h>
[9c0a9b3]55
56#include <arch/bios/bios.h>
57
[1e9a463]58#include <arch/mm/memory_init.h>
[fcfac420]59#include <interrupt.h>
[23d22eb]60#include <arch/debugger.h>
[281b607]61#include <proc/thread.h>
62#include <syscall/syscall.h>
[41d33ac]63#include <console/console.h>
[ad36bd6]64
[26678e5]65#ifdef CONFIG_SMP
66#include <arch/smp/apic.h>
67#endif
68
[f07bba5]69void arch_pre_mm_init(void)
[f761f1eb]70{
71 pm_init();
72
73 if (config.cpu_active == 1) {
[dba84ff]74 bios_init();
[76cec1e]75 i8259_init(); /* PIC */
[f761f1eb]76 i8254_init(); /* hard clock */
[5dce48b9]77
[25d7709]78 exc_register(VECTOR_SYSCALL, "syscall", (iroutine) syscall);
[169587a]79
[5f85c91]80 #ifdef CONFIG_SMP
[fcfac420]81 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
[25d7709]82 (iroutine) tlb_shootdown_ipi);
[5f85c91]83 #endif /* CONFIG_SMP */
[f761f1eb]84 }
85}
86
[6ba143d]87void arch_post_mm_init(void)
[7eade45]88{
[425913b]89 if (config.cpu_active == 1) {
[22cf454d]90
91#ifdef CONFIG_FB
[381465e]92 if (vesa_present())
93 vesa_init();
[22cf454d]94 else
95#endif
[381465e]96 ega_init(); /* video */
[22cf454d]97
98
[23d22eb]99 /* Enable debugger */
100 debugger_init();
[381465e]101 /* Merge all memory zones to 1 big zone */
102 zone_merge_all();
[babcb148]103 }
104}
105
[26678e5]106void arch_post_cpu_init()
107{
108#ifdef CONFIG_SMP
109 if (config.cpu_active > 1) {
110 l_apic_init();
111 l_apic_debug();
112 }
113#endif
114}
115
[7453929]116void arch_pre_smp_init(void)
[babcb148]117{
118 if (config.cpu_active == 1) {
[1e9a463]119 memory_print_map();
120
[5f85c91]121 #ifdef CONFIG_SMP
[85bfdcc8]122 acpi_init();
[5f85c91]123 #endif /* CONFIG_SMP */
[425913b]124 }
[7eade45]125}
126
[7453929]127void arch_post_smp_init(void)
128{
[a83a802]129 i8042_init(); /* keyboard controller */
[7453929]130}
131
[f761f1eb]132void calibrate_delay_loop(void)
133{
134 i8254_calibrate_delay_loop();
[f701b236]135 if (config.cpu_active == 1) {
136 /*
137 * This has to be done only on UP.
138 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
139 */
140 i8254_normal_operation();
141 }
[f761f1eb]142}
[281b607]143
[e1be3b6]144/** Set thread-local-storage pointer
[281b607]145 *
[3b712407]146 * TLS pointer is set in GS register. That means, the GS contains
147 * selector, and the descriptor->base is the correct address.
[281b607]148 */
[7f1c620]149unative_t sys_tls_set(unative_t addr)
[281b607]150{
[a6d4ceb]151 THREAD->arch.tls = addr;
[281b607]152 set_tls_desc(addr);
153
154 return 0;
155}
[41d33ac]156
157/** Acquire console back for kernel
158 *
159 */
160void arch_grab_console(void)
161{
162 i8042_grab();
163}
164/** Return console to userspace
165 *
166 */
167void arch_release_console(void)
168{
169 i8042_release();
170}
[b45c443]171
[06e1e95]172/** @}
[b45c443]173 */
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