source: mainline/kernel/arch/ia32/src/ia32.c@ 26678e5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 26678e5 was 26678e5, checked in by Jakub Jermar <jakub@…>, 19 years ago

Make SMP related parts of main.c more generic.
Move initialization of local APIC to architecture specific code.
Add arch_post_cpu_init() to support the above.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36
37#include <arch/types.h>
38#include <typedefs.h>
39
40#include <arch/pm.h>
41
42#include <arch/drivers/ega.h>
43#include <arch/drivers/vesa.h>
44#include <genarch/kbd/i8042.h>
45#include <arch/drivers/i8254.h>
46#include <arch/drivers/i8259.h>
47
48#include <arch/context.h>
49
50#include <config.h>
51
52#include <arch/interrupt.h>
53#include <arch/asm.h>
54#include <genarch/acpi/acpi.h>
55
56#include <arch/bios/bios.h>
57
58#include <arch/mm/memory_init.h>
59#include <interrupt.h>
60#include <arch/debugger.h>
61#include <proc/thread.h>
62#include <syscall/syscall.h>
63#include <console/console.h>
64
65#ifdef CONFIG_SMP
66#include <arch/smp/apic.h>
67#endif
68
69void arch_pre_mm_init(void)
70{
71 pm_init();
72
73 if (config.cpu_active == 1) {
74 bios_init();
75 i8259_init(); /* PIC */
76 i8254_init(); /* hard clock */
77
78 exc_register(VECTOR_SYSCALL, "syscall", (iroutine) syscall);
79
80 #ifdef CONFIG_SMP
81 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
82 (iroutine) tlb_shootdown_ipi);
83 #endif /* CONFIG_SMP */
84 }
85}
86
87void arch_post_mm_init(void)
88{
89 if (config.cpu_active == 1) {
90
91#ifdef CONFIG_FB
92 if (vesa_present())
93 vesa_init();
94 else
95#endif
96 ega_init(); /* video */
97
98
99 /* Enable debugger */
100 debugger_init();
101 /* Merge all memory zones to 1 big zone */
102 zone_merge_all();
103 }
104}
105
106void arch_post_cpu_init()
107{
108#ifdef CONFIG_SMP
109 if (config.cpu_active > 1) {
110 l_apic_init();
111 l_apic_debug();
112 }
113#endif
114}
115
116void arch_pre_smp_init(void)
117{
118 if (config.cpu_active == 1) {
119 memory_print_map();
120
121 #ifdef CONFIG_SMP
122 acpi_init();
123 #endif /* CONFIG_SMP */
124 }
125}
126
127void arch_post_smp_init(void)
128{
129 i8042_init(); /* keyboard controller */
130}
131
132void calibrate_delay_loop(void)
133{
134 i8254_calibrate_delay_loop();
135 if (config.cpu_active == 1) {
136 /*
137 * This has to be done only on UP.
138 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
139 */
140 i8254_normal_operation();
141 }
142}
143
144/** Set thread-local-storage pointer
145 *
146 * TLS pointer is set in GS register. That means, the GS contains
147 * selector, and the descriptor->base is the correct address.
148 */
149unative_t sys_tls_set(unative_t addr)
150{
151 THREAD->arch.tls = addr;
152 set_tls_desc(addr);
153
154 return 0;
155}
156
157/** Acquire console back for kernel
158 *
159 */
160void arch_grab_console(void)
161{
162 i8042_grab();
163}
164/** Return console to userspace
165 *
166 */
167void arch_release_console(void)
168{
169 i8042_release();
170}
171
172/** @}
173 */
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