source: mainline/kernel/arch/ia32/include/mm/page.h@ 973ef9fc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 973ef9fc was dc0b964, checked in by Martin Decky <martin@…>, 15 years ago
  • do not hardwire PRI??? formatting macros in the sources, use autotool to detect the correct values
  • use autotool to detect correct values for integer literal macros (UINT32_C, etc.)
  • start using portable UINT??_C style macros for integer constants
  • Property mode set to 100644
File size: 6.2 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[17ccb9d7]29/** @addtogroup ia32mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_ia32_PAGE_H_
36#define KERN_ia32_PAGE_H_
[f761f1eb]37
[d1f8a87]38#include <arch/mm/frame.h>
[7a0359b]39#include <trace.h>
[d1f8a87]40
[dc0b964]41#define PAGE_WIDTH FRAME_WIDTH
42#define PAGE_SIZE FRAME_SIZE
[f761f1eb]43
[d1f8a87]44#ifdef KERNEL
45
[8f2153b]46#ifndef __ASM__
[dc0b964]47
48#define KA2PA(x) (((uintptr_t) (x)) - UINT32_C(0x80000000))
49#define PA2KA(x) (((uintptr_t) (x)) + UINT32_C(0x80000000))
50
51#else /* __ASM__ */
52
53#define KA2PA(x) ((x) - 0x80000000)
54#define PA2KA(x) ((x) + 0x80000000)
55
56#endif /* __ASM__ */
[f761f1eb]57
[992bbb97]58/*
59 * Implementation of generic 4-level page table interface.
60 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
61 */
[c03ee1c]62
63/* Number of entries in each level. */
[dc0b964]64#define PTL0_ENTRIES_ARCH 1024
65#define PTL1_ENTRIES_ARCH 0
66#define PTL2_ENTRIES_ARCH 0
67#define PTL3_ENTRIES_ARCH 1024
[ecbdc724]68
[c03ee1c]69/* Page table sizes for each level. */
[dc0b964]70#define PTL0_SIZE_ARCH ONE_FRAME
71#define PTL1_SIZE_ARCH 0
72#define PTL2_SIZE_ARCH 0
73#define PTL3_SIZE_ARCH ONE_FRAME
[6b781c0]74
[c03ee1c]75/* Macros calculating indices for each level. */
[dc0b964]76#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ffU)
77#define PTL1_INDEX_ARCH(vaddr) 0
78#define PTL2_INDEX_ARCH(vaddr) 0
79#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ffU)
[992bbb97]80
[c03ee1c]81/* Get PTE address accessors for each level. */
82#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
83 ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12))
84#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
85 (ptl1)
86#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
87 (ptl2)
88#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
89 ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12))
90
91/* Set PTE address accessors for each level. */
92#define SET_PTL0_ADDRESS_ARCH(ptl0) \
93 (write_cr3((uintptr_t) (ptl0)))
94#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
95 (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12)
[ff9f858]96#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
97#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
[c03ee1c]98#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
99 (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12)
100
101/* Get PTE flags accessors for each level. */
102#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
[98000fb]103 get_pt_flags((pte_t *) (ptl0), (size_t) (i))
[c03ee1c]104#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
105 PAGE_PRESENT
106#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
107 PAGE_PRESENT
108#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
[98000fb]109 get_pt_flags((pte_t *) (ptl3), (size_t) (i))
[c03ee1c]110
111/* Set PTE flags accessors for each level. */
[17ccb9d7]112#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
[98000fb]113 set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
[ff9f858]114#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
115#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
[c03ee1c]116#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
[98000fb]117 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
[c03ee1c]118
119/* Macros for querying the last level entries. */
120#define PTE_VALID_ARCH(p) \
121 (*((uint32_t *) (p)) != 0)
122#define PTE_PRESENT_ARCH(p) \
123 ((p)->present != 0)
124#define PTE_GET_FRAME_ARCH(p) \
125 ((p)->frame_address << FRAME_WIDTH)
126#define PTE_WRITABLE_ARCH(p) \
127 ((p)->writeable != 0)
[dc0b964]128#define PTE_EXECUTABLE_ARCH(p) 1
[ecbdc724]129
[8f2153b]130#ifndef __ASM__
131
[b3f8fb7]132#include <mm/mm.h>
133#include <arch/interrupt.h>
[f4c2b6a]134#include <typedefs.h>
[8f2153b]135
[567807b1]136/* Page fault error codes. */
137
[c03ee1c]138/** When bit on this position is 0, the page fault was caused by a not-present
139 * page.
140 */
[b3f8fb7]141#define PFERR_CODE_P (1 << 0)
[567807b1]142
143/** When bit on this position is 1, the page fault was caused by a write. */
[b3f8fb7]144#define PFERR_CODE_RW (1 << 1)
[567807b1]145
146/** When bit on this position is 1, the page fault was caused in user mode. */
[b3f8fb7]147#define PFERR_CODE_US (1 << 2)
[567807b1]148
149/** When bit on this position is 1, a reserved bit was set in page directory. */
[dc0b964]150#define PFERR_CODE_RSVD (1 << 3)
[f761f1eb]151
[0eef314]152/** Page Table Entry. */
153typedef struct {
154 unsigned present : 1;
155 unsigned writeable : 1;
156 unsigned uaccessible : 1;
157 unsigned page_write_through : 1;
158 unsigned page_cache_disable : 1;
159 unsigned accessed : 1;
160 unsigned dirty : 1;
161 unsigned pat : 1;
162 unsigned global : 1;
163 unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */
164 unsigned avl : 2;
165 unsigned frame_address : 20;
166} __attribute__ ((packed)) pte_t;
167
[7a0359b]168NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
[ff9f858]169{
170 pte_t *p = &pt[i];
171
[c03ee1c]172 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
173 (!p->present) << PAGE_PRESENT_SHIFT |
174 p->uaccessible << PAGE_USER_SHIFT |
175 1 << PAGE_READ_SHIFT |
176 p->writeable << PAGE_WRITE_SHIFT |
177 1 << PAGE_EXEC_SHIFT |
178 p->global << PAGE_GLOBAL_SHIFT);
[ff9f858]179}
180
[7a0359b]181NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
[ff9f858]182{
183 pte_t *p = &pt[i];
184
185 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
186 p->present = !(flags & PAGE_NOT_PRESENT);
[51029384]187 p->uaccessible = (flags & PAGE_USER) != 0;
188 p->writeable = (flags & PAGE_WRITE) != 0;
[bfb87df]189 p->global = (flags & PAGE_GLOBAL) != 0;
[0882a9a]190
191 /*
[c03ee1c]192 * Ensure that there is at least one bit set even if the present bit is
193 * cleared.
[0882a9a]194 */
195 p->soft_valid = true;
[ff9f858]196}
[992bbb97]197
[f761f1eb]198extern void page_arch_init(void);
[214ec25c]199extern void page_fault(unsigned int, istate_t *);
[f761f1eb]200
[8f2153b]201#endif /* __ASM__ */
202
[d1f8a87]203#endif /* KERNEL */
204
[f761f1eb]205#endif
[b45c443]206
[06e1e95]207/** @}
[b45c443]208 */
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