source: mainline/kernel/arch/ia32/include/cpu.h@ 2ee1ccc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2ee1ccc was 49e6c6b4, checked in by Adam Hraska <adam.hraska+hos@…>, 13 years ago

ipi: Added support for unicast IPI on amd64, ia32.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia32_CPU_H_
36#define KERN_ia32_CPU_H_
37
38#define EFLAGS_IF (1 << 9)
39#define EFLAGS_DF (1 << 10)
40#define EFLAGS_NT (1 << 14)
41#define EFLAGS_RF (1 << 16)
42
43#define CR4_OSFXSR_MASK (1<<9)
44
45/* Support for SYSENTER and SYSEXIT */
46#define IA32_MSR_SYSENTER_CS 0x174U
47#define IA32_MSR_SYSENTER_ESP 0x175U
48#define IA32_MSR_SYSENTER_EIP 0x176U
49
50#ifndef __ASM__
51
52#include <arch/pm.h>
53#include <arch/asm.h>
54#include <arch/cpuid.h>
55
56typedef struct {
57 unsigned int vendor;
58 unsigned int family;
59 unsigned int model;
60 unsigned int stepping;
61 cpuid_feature_info fi;
62
63 unsigned int id; /** CPU's local, ie physical, APIC ID. */
64
65 tss_t *tss;
66
67 size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
68} cpu_arch_t;
69
70#endif
71
72#endif
73
74/** @}
75 */
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