source: mainline/kernel/arch/arm64/src/fpu.S

Last change on this file was 84176f3, checked in by Jakub Jermář <jakub@…>, 6 years ago

arm64: Add support for the architecture

This changeset adds basic support to run HelenOS on AArch64, targeting
the QEMU virt platform.

Boot:

  • Boot relies on the EDK II firmware, GRUB2 for EFI and the HelenOS bootloader (UEFI application). EDK II loads GRUB2 from a CD, GRUB2 loads the HelenOS bootloader (via UEFI) which loads OS components.
  • UEFI applications use the PE/COFF format and must be relocatable. The first problem is solved by manually having the PE/COFF headers and tables written in assembler. The relocatable requirement is addressed by compiling the code with -fpic and having the bootloader relocate itself at its startup.

Kernel:

  • Kernel code for AArch64 consists mostly of stubbing out various architecture-specific hooks: virtual memory management, interrupt and exception handling, context switching (including FPU lazy switching), support for virtual timer, atomic sequences and barriers, cache and TLB maintenance, thread and process initialization.
  • The patch adds a kernel driver for GICv2 (interrupt controller).
  • The PL011 kernel driver is extended to allow userspace to take ownership of the console.
  • The current code is not able to dynamically obtain information about available devices on the underlying machine. The port instead implements a machine-func interface similar to the one implemented by arm32. It defines a machine for the QEMU AArch64 virt platform. The configuration (device addresses and IRQ numbers) is then baked into the machine definition.

User space:

  • Uspace code for AArch64 similarly mostly implements architecture-specific hooks: context saving/restoring, syscall support, TLS support.

The patchset allows to boot the system but user interaction with the OS
is not yet possible.
  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * Copyright (c) 2018 Petr Pavlu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <abi/asmtool.h>
30#include <arch/fpu_context_struct.h>
31
32.text
33
34FUNCTION_BEGIN(fpu_context_save)
35 /* Save FPU registers into fpu_context_t pointed by x0. */
36 stp q0, q1, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 0]
37 stp q2, q3, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 2]
38 stp q4, q5, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 4]
39 stp q6, q7, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 6]
40 stp q8, q9, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 8]
41 stp q10, q11, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 10]
42 stp q12, q13, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 12]
43 stp q14, q15, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 14]
44 stp q16, q17, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 16]
45 stp q18, q19, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 18]
46 stp q20, q21, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 20]
47 stp q22, q23, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 22]
48 stp q24, q25, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 24]
49 stp q26, q27, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 26]
50 stp q28, q29, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 28]
51 stp q30, q31, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 30]
52 mrs x1, fpcr
53 str w1, [x0, #FPU_CONTEXT_OFFSET_FPCR]
54 mrs x1, fpsr
55 str w1, [x0, #FPU_CONTEXT_OFFSET_FPSR]
56 ret
57FUNCTION_END(fpu_context_save)
58
59FUNCTION_BEGIN(fpu_context_restore)
60 /* Restore FPU registers from fpu_context_t pointed by x0. */
61 ldp q0, q1, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 0]
62 ldp q2, q3, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 2]
63 ldp q4, q5, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 4]
64 ldp q6, q7, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 6]
65 ldp q8, q9, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 8]
66 ldp q10, q11, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 10]
67 ldp q12, q13, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 12]
68 ldp q14, q15, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 14]
69 ldp q16, q17, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 16]
70 ldp q18, q19, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 18]
71 ldp q20, q21, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 20]
72 ldp q22, q23, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 22]
73 ldp q24, q25, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 24]
74 ldp q26, q27, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 26]
75 ldp q28, q29, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 28]
76 ldp q30, q31, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 30]
77 ldr w1, [x0, #FPU_CONTEXT_OFFSET_FPCR]
78 msr fpcr, x1
79 ldr w1, [x0, #FPU_CONTEXT_OFFSET_FPSR]
80 msr fpsr, x1
81 ret
82FUNCTION_END(fpu_context_restore)
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