[84176f3] | 1 | /*
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| 2 | * Copyright (c) 2018 Petr Pavlu
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <abi/asmtool.h>
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| 30 | #include <arch/fpu_context_struct.h>
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| 31 |
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| 32 | .text
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| 33 |
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| 34 | FUNCTION_BEGIN(fpu_context_save)
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| 35 | /* Save FPU registers into fpu_context_t pointed by x0. */
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| 36 | stp q0, q1, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 0]
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| 37 | stp q2, q3, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 2]
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| 38 | stp q4, q5, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 4]
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| 39 | stp q6, q7, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 6]
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| 40 | stp q8, q9, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 8]
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| 41 | stp q10, q11, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 10]
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| 42 | stp q12, q13, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 12]
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| 43 | stp q14, q15, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 14]
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| 44 | stp q16, q17, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 16]
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| 45 | stp q18, q19, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 18]
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| 46 | stp q20, q21, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 20]
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| 47 | stp q22, q23, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 22]
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| 48 | stp q24, q25, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 24]
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| 49 | stp q26, q27, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 26]
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| 50 | stp q28, q29, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 28]
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| 51 | stp q30, q31, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 30]
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| 52 | mrs x1, fpcr
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| 53 | str w1, [x0, #FPU_CONTEXT_OFFSET_FPCR]
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| 54 | mrs x1, fpsr
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| 55 | str w1, [x0, #FPU_CONTEXT_OFFSET_FPSR]
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| 56 | ret
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| 57 | FUNCTION_END(fpu_context_save)
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| 58 |
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| 59 | FUNCTION_BEGIN(fpu_context_restore)
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| 60 | /* Restore FPU registers from fpu_context_t pointed by x0. */
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| 61 | ldp q0, q1, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 0]
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| 62 | ldp q2, q3, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 2]
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| 63 | ldp q4, q5, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 4]
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| 64 | ldp q6, q7, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 6]
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| 65 | ldp q8, q9, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 8]
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| 66 | ldp q10, q11, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 10]
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| 67 | ldp q12, q13, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 12]
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| 68 | ldp q14, q15, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 14]
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| 69 | ldp q16, q17, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 16]
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| 70 | ldp q18, q19, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 18]
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| 71 | ldp q20, q21, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 20]
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| 72 | ldp q22, q23, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 22]
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| 73 | ldp q24, q25, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 24]
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| 74 | ldp q26, q27, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 26]
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| 75 | ldp q28, q29, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 28]
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| 76 | ldp q30, q31, [x0, #FPU_CONTEXT_OFFSET_VREGS + 16 * 30]
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| 77 | ldr w1, [x0, #FPU_CONTEXT_OFFSET_FPCR]
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| 78 | msr fpcr, x1
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| 79 | ldr w1, [x0, #FPU_CONTEXT_OFFSET_FPSR]
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| 80 | msr fpsr, x1
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| 81 | ret
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| 82 | FUNCTION_END(fpu_context_restore)
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