| 1 | /*
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| 2 | * Copyright (c) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <align.h>
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| 30 | #include <arch/cp15.h>
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| 31 | #include <arch/cache.h>
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| 32 | #include <arch/barrier.h>
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| 33 | #include <barrier.h>
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| 34 |
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| 35 | /*
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| 36 | * There are multiple ways ICache can be implemented on ARM machines. Namely
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| 37 | * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
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| 38 | * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum
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| 39 | * compatibility across processors, ARM recommends that operating systems target
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| 40 | * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
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| 41 | * and do not assume the presence of the IVIPT extension. Software that relies
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| 42 | * on the IVIPT extension might fail in an unpredictable way on an ARMv7
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| 43 | * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
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| 44 | * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
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| 45 | *
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| 46 | * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
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| 47 | * maintenance to other places than just smc.
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| 48 | */
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| 49 |
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| 50 | // TODO: Determine CP15_C7_MVA_ALIGN dynamically
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| 51 |
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| 52 | void smc_coherence(void *a, size_t l)
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| 53 | {
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| 54 | uintptr_t end = (uintptr_t) a + l;
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| 55 | uintptr_t begin = ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN);
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| 56 |
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| 57 | for (uintptr_t addr = begin; addr < end; addr += CP15_C7_MVA_ALIGN) {
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| 58 | dcache_clean_mva_pou(addr);
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| 59 | }
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| 60 |
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| 61 | /* Wait for completion */
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| 62 | dsb();
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| 63 |
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| 64 | icache_invalidate();
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| 65 | dsb();
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| 66 | /* Wait for Inst refetch */
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| 67 | isb();
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| 68 | }
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