| 1 | /*
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| 2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup arm32mm
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Page fault related functions.
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| 34 | */
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| 35 | #include <panic.h>
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| 36 | #include <arch/exception.h>
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| 37 | #include <arch/mm/page_fault.h>
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| 38 | #include <mm/as.h>
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| 39 | #include <genarch/mm/page_pt.h>
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| 40 | #include <arch.h>
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| 41 | #include <interrupt.h>
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| 42 | #include <print.h>
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| 43 |
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| 44 | /** Returns value stored in fault status register.
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| 45 | *
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| 46 | * @return Value stored in CP15 fault status register (FSR).
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| 47 | */
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| 48 | static inline fault_status_t read_fault_status_register(void)
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| 49 | {
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| 50 | fault_status_union_t fsu;
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| 51 |
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| 52 | /* fault status is stored in CP15 register 5 */
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| 53 | asm volatile (
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| 54 | "mrc p15, 0, %[dummy], c5, c0, 0"
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| 55 | : [dummy] "=r" (fsu.dummy)
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| 56 | );
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| 57 |
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| 58 | return fsu.fs;
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| 59 | }
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| 60 |
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| 61 | /** Returns FAR (fault address register) content.
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| 62 | *
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| 63 | * @return FAR (fault address register) content (address that caused a page
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| 64 | * fault)
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| 65 | */
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| 66 | static inline uintptr_t read_fault_address_register(void)
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| 67 | {
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| 68 | uintptr_t ret;
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| 69 |
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| 70 | /* fault adress is stored in CP15 register 6 */
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| 71 | asm volatile (
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| 72 | "mrc p15, 0, %[ret], c6, c0, 0"
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| 73 | : [ret] "=r" (ret)
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| 74 | );
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| 75 |
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| 76 | return ret;
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| 77 | }
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| 78 |
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| 79 | /** Decides whether the instruction is load/store or not.
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| 80 | *
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| 81 | * @param instr Instruction
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| 82 | *
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| 83 | * @return true when instruction is load/store, false otherwise
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| 84 | *
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| 85 | */
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| 86 | static inline bool is_load_store_instruction(instruction_t instr)
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| 87 | {
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| 88 | /* load store immediate offset */
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| 89 | if (instr.type == 0x2)
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| 90 | return true;
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| 91 |
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| 92 | /* load store register offset */
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| 93 | if ((instr.type == 0x3) && (instr.bit4 == 0))
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| 94 | return true;
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| 95 |
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| 96 | /* load store multiple */
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| 97 | if (instr.type == 0x4)
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| 98 | return true;
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| 99 |
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| 100 | /* oprocessor load/store */
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| 101 | if (instr.type == 0x6)
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| 102 | return true;
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| 103 |
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| 104 | return false;
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| 105 | }
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| 106 |
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| 107 | /** Decides whether the instruction is swap or not.
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| 108 | *
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| 109 | * @param instr Instruction
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| 110 | *
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| 111 | * @return true when instruction is swap, false otherwise
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| 112 | */
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| 113 | static inline bool is_swap_instruction(instruction_t instr)
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| 114 | {
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| 115 | /* swap, swapb instruction */
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| 116 | if ((instr.type == 0x0) &&
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| 117 | ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
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| 118 | (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
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| 119 | return true;
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| 120 |
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| 121 | return false;
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| 122 | }
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| 123 |
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| 124 | /** Decides whether read or write into memory is requested.
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| 125 | *
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| 126 | * @param instr_addr Address of instruction which tries to access memory.
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| 127 | * @param badvaddr Virtual address the instruction tries to access.
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| 128 | *
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| 129 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
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| 130 | * requested.
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| 131 | */
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| 132 | static pf_access_t get_memory_access_type(uint32_t instr_addr,
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| 133 | uintptr_t badvaddr)
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| 134 | {
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| 135 | instruction_union_t instr_union;
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| 136 | instr_union.pc = instr_addr;
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| 137 |
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| 138 | instruction_t instr = *(instr_union.instr);
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| 139 |
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| 140 | /* undefined instructions */
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| 141 | if (instr.condition == 0xf) {
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| 142 | panic("page_fault - instruction does not access memory "
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| 143 | "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
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| 144 | instr_union.pc, (void *) badvaddr);
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| 145 | return PF_ACCESS_EXEC;
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| 146 | }
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| 147 |
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| 148 | /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
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| 149 | * A5.3 (PDF p. 206) */
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| 150 | static const struct {
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| 151 | uint32_t mask;
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| 152 | uint32_t value;
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| 153 | pf_access_t access;
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| 154 | } ls_inst[] = {
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| 155 | /* Store word/byte */
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| 156 | { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /*STR(B) imm*/
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| 157 | { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /*STR(B) reg*/
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| 158 | /* Load word/byte */
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| 159 | { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /*LDR imm*/
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| 160 | { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /*LDR reg*/
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| 161 | /* Store half-word/dual A5.2.8 */
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| 162 | { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/
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| 163 | /* Load half-word/dual A5.2.8 */
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| 164 | { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/
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| 165 | { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/
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| 166 | /* Block data transfer, Store */
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| 167 | { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */
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| 168 | { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */
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| 169 | /* Swap */
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| 170 | { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
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| 171 | };
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| 172 | pf_access_t access = PF_ACCESS_UNKNOWN;
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| 173 | uint32_t inst = *(uint32_t*)instr_addr;
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| 174 | for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
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| 175 | if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
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| 176 | if (access != PF_ACCESS_UNKNOWN)
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| 177 | printf("Double match: %x %u\n", inst, i);
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| 178 | access = ls_inst[i].access;
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| 179 | }
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| 180 | }
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| 181 |
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| 182 | /* load store instructions */
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| 183 | if (is_load_store_instruction(instr)) {
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| 184 | if (instr.access == 1) {
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| 185 | if (access != PF_ACCESS_READ)
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| 186 | printf("MISMATCH READ(%u): %x\n", access, inst);
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| 187 | return PF_ACCESS_READ;
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| 188 | } else {
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| 189 | if (access != PF_ACCESS_WRITE)
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| 190 | printf("MISMATCH WRITE(%u): %x\n", access, inst);
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| 191 | return PF_ACCESS_WRITE;
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| 192 | }
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| 193 | }
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| 194 |
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| 195 | /* swap, swpb instruction */
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| 196 | if (is_swap_instruction(instr)) {
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| 197 | if (access != PF_ACCESS_WRITE)
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| 198 | printf("MISMATCH WRITE(%u): %x\n", access, inst);
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| 199 | return PF_ACCESS_WRITE;
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| 200 | }
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| 201 |
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| 202 | panic("page_fault - instruction doesn't access memory "
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| 203 | "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
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| 204 | instr_union.pc, (void *) badvaddr);
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| 205 |
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| 206 | return PF_ACCESS_EXEC;
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| 207 | }
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| 208 |
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| 209 | /** Handles "data abort" exception (load or store at invalid address).
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| 210 | *
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| 211 | * @param exc_no Exception number.
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| 212 | * @param istate CPU state when exception occured.
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| 213 | *
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| 214 | */
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| 215 | void data_abort(unsigned int exc_no, istate_t *istate)
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| 216 | {
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| 217 | fault_status_t fsr __attribute__ ((unused)) =
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| 218 | read_fault_status_register();
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| 219 | uintptr_t badvaddr = read_fault_address_register();
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| 220 |
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| 221 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
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| 222 |
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| 223 | int ret = as_page_fault(badvaddr, access, istate);
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| 224 |
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| 225 | if (ret == AS_PF_FAULT) {
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| 226 | fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
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| 227 | panic_memtrap(istate, access, badvaddr, NULL);
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| 228 | }
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| 229 | }
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| 230 |
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| 231 | /** Handles "prefetch abort" exception (instruction couldn't be executed).
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| 232 | *
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| 233 | * @param exc_no Exception number.
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| 234 | * @param istate CPU state when exception occured.
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| 235 | *
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| 236 | */
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| 237 | void prefetch_abort(unsigned int exc_no, istate_t *istate)
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| 238 | {
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| 239 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
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| 240 |
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| 241 | if (ret == AS_PF_FAULT) {
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| 242 | fault_if_from_uspace(istate,
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| 243 | "Page fault - prefetch_abort: %#x.", istate->pc);
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| 244 | panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, NULL);
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| 245 | }
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| 246 | }
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| 247 |
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| 248 | /** @}
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| 249 | */
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