source: mainline/kernel/arch/arm32/src/mm/page_fault.c

Last change on this file was d1582b50, checked in by Jiri Svoboda <jiri@…>, 5 years ago

Fix spacing in single-line comments using latest ccheck

This found incorrectly formatted section comments (with blocks of
asterisks or dashes). I strongly believe against using section comments
but I am not simply removing them since that would probably be
controversial.
  • Property mode set to 100644
File size: 8.9 KB
Line 
1/*
2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_arm32_mm
30 * @{
31 */
32/** @file
33 * @brief Page fault related functions.
34 */
35#include <panic.h>
36#include <arch/cp15.h>
37#include <arch/exception.h>
38#include <arch/mm/page_fault.h>
39#include <mm/as.h>
40#include <genarch/mm/page_pt.h>
41#include <arch.h>
42#include <interrupt.h>
43
44/**
45 * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
46 *
47 * B3.13.3 page B3-1406 (PDF page 1406)
48 */
49typedef enum {
50 DFSR_SOURCE_ALIGN = 0x0001,
51 DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
52 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
53 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
54 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
55 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
56 DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
57 DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
58 DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */
59 DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
60 DFSR_SOURCE_DOMAIN_L1 = 0x0009,
61 DFSR_SOURCE_DOMAIN_L2 = 0x000b,
62 DFSR_SOURCE_PERMISSION_L1 = 0x000d,
63 DFSR_SOURCE_PERMISSION_L2 = 0x000f,
64 DFSR_SOURCE_DEBUG = 0x0002,
65 DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
66 DFSR_SOURCE_TLB_CONFLICT = 0x0400,
67 DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
68 DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
69 DFSR_SOURCE_SYNC_PARITY = 0x0409,
70 DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
71 DFSR_SOURCE_ASYNC_PARITY = 0x0408,
72 DFSR_SOURCE_MASK = 0x0000040f,
73} dfsr_source_t;
74
75static inline const char *dfsr_source_to_str(dfsr_source_t source)
76{
77 switch (source) {
78 case DFSR_SOURCE_TRANSLATION_L1:
79 return "Translation fault L1";
80 case DFSR_SOURCE_TRANSLATION_L2:
81 return "Translation fault L2";
82 case DFSR_SOURCE_PERMISSION_L1:
83 return "Permission fault L1";
84 case DFSR_SOURCE_PERMISSION_L2:
85 return "Permission fault L2";
86 case DFSR_SOURCE_ALIGN:
87 return "Alignment fault";
88 case DFSR_SOURCE_CACHE_MAINTENANCE:
89 return "Instruction cache maintenance fault";
90 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
91 return "Synchronous external abort on translation table walk level 1";
92 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
93 return "Synchronous external abort on translation table walk level 2";
94 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
95 return "Synchronous parity error on translation table walk level 1";
96 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
97 return "Synchronous parity error on translation table walk level 2";
98 case DFSR_SOURCE_ACCESS_FLAG_L1:
99 return "Access flag fault L1";
100 case DFSR_SOURCE_ACCESS_FLAG_L2:
101 return "Access flag fault L2";
102 case DFSR_SOURCE_DOMAIN_L1:
103 return "Domain fault L1";
104 case DFSR_SOURCE_DOMAIN_L2:
105 return "Domain flault L2";
106 case DFSR_SOURCE_DEBUG:
107 return "Debug event";
108 case DFSR_SOURCE_SYNC_EXTERNAL:
109 return "Synchronous external abort";
110 case DFSR_SOURCE_TLB_CONFLICT:
111 return "TLB conflict abort";
112 case DFSR_SOURCE_LOCKDOWN:
113 return "Lockdown (Implementation defined)";
114 case DFSR_SOURCE_COPROCESSOR:
115 return "Coprocessor abort (Implementation defined)";
116 case DFSR_SOURCE_SYNC_PARITY:
117 return "Synchronous parity error on memory access";
118 case DFSR_SOURCE_ASYNC_EXTERNAL:
119 return "Asynchronous external abort";
120 case DFSR_SOURCE_ASYNC_PARITY:
121 return "Asynchronous parity error on memory access";
122 case DFSR_SOURCE_MASK:
123 break;
124 }
125 return "Unknown data abort";
126}
127
128#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
129/** Decides whether read or write into memory is requested.
130 *
131 * @param instr_addr Address of instruction which tries to access memory.
132 * @param badvaddr Virtual address the instruction tries to access.
133 *
134 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
135 * requested.
136 */
137static pf_access_t get_memory_access_type(uint32_t instr_addr,
138 uintptr_t badvaddr)
139{
140 instruction_union_t instr_union;
141 instr_union.pc = instr_addr;
142
143 instruction_t instr = *(instr_union.instr);
144
145 /* undefined instructions */
146 if (instr.condition == 0xf) {
147 panic("page_fault - instruction does not access memory "
148 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
149 *(uint32_t *)instr_union.instr, (void *) badvaddr);
150 return PF_ACCESS_EXEC;
151 }
152
153 /*
154 * See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
155 * A5.3 (PDF p. 206)
156 */
157 static const struct {
158 uint32_t mask;
159 uint32_t value;
160 pf_access_t access;
161 } ls_inst[] = {
162 /* Store word/byte */
163 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /* STR(B) imm */
164 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /* STR(B) reg */
165 /* Load word/byte */
166 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /* LDR(B) imm */
167 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /* LDR(B) reg */
168 /* Store half-word/dual A5.2.8 */
169 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /* STRH imm reg */
170 /* Load half-word/dual A5.2.8 */
171 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /* LDRH imm reg */
172 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /* LDRH imm reg */
173 /* Block data transfer, Store */
174 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */
175 { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */
176 /* Swap */
177 { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
178 };
179 const uint32_t inst = *(uint32_t *)instr_addr;
180 for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
181 if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
182 return ls_inst[i].access;
183 }
184 }
185
186 panic("page_fault - instruction doesn't access memory "
187 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
188 inst, (void *) badvaddr);
189}
190#endif
191
192/** Handles "data abort" exception (load or store at invalid address).
193 *
194 * @param exc_no Exception number.
195 * @param istate CPU state when exception occured.
196 *
197 */
198void data_abort(unsigned int exc_no, istate_t *istate)
199{
200 const uintptr_t badvaddr = DFAR_read();
201 const fault_status_t fsr = { .raw = DFSR_read() };
202 const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
203
204 switch (source) {
205 case DFSR_SOURCE_TRANSLATION_L1:
206 case DFSR_SOURCE_TRANSLATION_L2:
207 case DFSR_SOURCE_PERMISSION_L1:
208 case DFSR_SOURCE_PERMISSION_L2:
209 /* Page fault is handled further down */
210 break;
211 case DFSR_SOURCE_ALIGN:
212 case DFSR_SOURCE_CACHE_MAINTENANCE:
213 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
214 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
215 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
216 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
217 case DFSR_SOURCE_ACCESS_FLAG_L1:
218 case DFSR_SOURCE_ACCESS_FLAG_L2:
219 case DFSR_SOURCE_DOMAIN_L1:
220 case DFSR_SOURCE_DOMAIN_L2:
221 case DFSR_SOURCE_DEBUG:
222 case DFSR_SOURCE_SYNC_EXTERNAL:
223 case DFSR_SOURCE_TLB_CONFLICT:
224 case DFSR_SOURCE_LOCKDOWN:
225 case DFSR_SOURCE_COPROCESSOR:
226 case DFSR_SOURCE_SYNC_PARITY:
227 case DFSR_SOURCE_ASYNC_EXTERNAL:
228 case DFSR_SOURCE_ASYNC_PARITY:
229 case DFSR_SOURCE_MASK:
230 /* Weird abort stuff */
231 fault_if_from_uspace(istate, "Unhandled abort %s at address: "
232 "%#x.", dfsr_source_to_str(source), badvaddr);
233 panic("Unhandled abort %s at address: %#x.",
234 dfsr_source_to_str(source), badvaddr);
235 }
236
237#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
238 const pf_access_t access =
239 fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
240#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
241 const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
242#else
243#error "Unsupported architecture"
244#endif
245 as_page_fault(badvaddr, access, istate);
246}
247
248/** Handles "prefetch abort" exception (instruction couldn't be executed).
249 *
250 * @param exc_no Exception number.
251 * @param istate CPU state when exception occured.
252 *
253 */
254void prefetch_abort(unsigned int exc_no, istate_t *istate)
255{
256 as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
257}
258
259/** @}
260 */
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