source: mainline/kernel/arch/arm32/src/mm/page_fault.c@ 1466a8f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 1466a8f was 9e96666, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

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1/*
2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32mm
30 * @{
31 */
32/** @file
33 * @brief Page fault related functions.
34 */
35#include <panic.h>
36#include <arch/exception.h>
37#include <arch/mm/page_fault.h>
38#include <mm/as.h>
39#include <genarch/mm/page_pt.h>
40#include <arch.h>
41#include <interrupt.h>
42#include <print.h>
43
44
45/**
46 * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
47 *
48 * B3.13.3 page B3-1406 (PDF page 1406)
49 */
50typedef enum {
51 DFSR_SOURCE_ALIGN = 0x0001,
52 DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
53 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
54 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
55 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
56 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
57 DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
58 DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
59 DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */
60 DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
61 DFSR_SOURCE_DOMAIN_L1 = 0x0009,
62 DFSR_SOURCE_DOMAIN_L2 = 0x000b,
63 DFSR_SOURCE_PERMISSION_L1 = 0x000d,
64 DFSR_SOURCE_PERMISSION_L2 = 0x000f,
65 DFSR_SOURCE_DEBUG = 0x0002,
66 DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
67 DFSR_SOURCE_TLB_CONFLICT = 0x0400,
68 DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
69 DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
70 DFSR_SOURCE_SYNC_PARITY = 0x0409,
71 DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
72 DFSR_SOURCE_ASYNC_PARITY = 0x0408,
73 DFSR_SOURCE_MASK = 0x0000040f,
74} dfsr_source_t;
75
76static inline const char * dfsr_source_to_str(dfsr_source_t source)
77{
78 switch (source) {
79 case DFSR_SOURCE_TRANSLATION_L1:
80 return "Translation fault L1";
81 case DFSR_SOURCE_TRANSLATION_L2:
82 return "Translation fault L2";
83 case DFSR_SOURCE_PERMISSION_L1:
84 return "Permission fault L1";
85 case DFSR_SOURCE_PERMISSION_L2:
86 return "Permission fault L2";
87 case DFSR_SOURCE_ALIGN:
88 return "Alignment fault";
89 case DFSR_SOURCE_CACHE_MAINTENANCE:
90 return "Instruction cache maintenance fault";
91 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
92 return "Synchronous external abort on translation table walk level 1";
93 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
94 return "Synchronous external abort on translation table walk level 2";
95 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
96 return "Synchronous parity error on translation table walk level 1";
97 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
98 return "Synchronous parity error on translation table walk level 2";
99 case DFSR_SOURCE_ACCESS_FLAG_L1:
100 return "Access flag fault L1";
101 case DFSR_SOURCE_ACCESS_FLAG_L2:
102 return "Access flag fault L2";
103 case DFSR_SOURCE_DOMAIN_L1:
104 return "Domain fault L1";
105 case DFSR_SOURCE_DOMAIN_L2:
106 return "Domain flault L2";
107 case DFSR_SOURCE_DEBUG:
108 return "Debug event";
109 case DFSR_SOURCE_SYNC_EXTERNAL:
110 return "Synchronous external abort";
111 case DFSR_SOURCE_TLB_CONFLICT:
112 return "TLB conflict abort";
113 case DFSR_SOURCE_LOCKDOWN:
114 return "Lockdown (Implementation defined)";
115 case DFSR_SOURCE_COPROCESSOR:
116 return "Coprocessor abort (Implementation defined)";
117 case DFSR_SOURCE_SYNC_PARITY:
118 return "Synchronous parity error on memory access";
119 case DFSR_SOURCE_ASYNC_EXTERNAL:
120 return "Asynchronous external abort";
121 case DFSR_SOURCE_ASYNC_PARITY:
122 return "Asynchronous parity error on memory access";
123 case DFSR_SOURCE_MASK:
124 break;
125 }
126 return "Unknown data abort";
127}
128
129
130/** Returns value stored in comnbined/data fault status register.
131 *
132 * @return Value stored in CP15 fault status register (FSR).
133 *
134 * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
135 * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
136 * the architecture. A write flag (bit[11] of the DFSR) has also been
137 * introduced."
138 * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
139 *
140 * See ch. B4.9.6 for location of data/instruction FSR.
141 *
142 */
143static inline fault_status_t read_data_fault_status_register(void)
144{
145 fault_status_t fsu;
146
147 /* Combined/Data fault status is stored in CP15 register 5, c0. */
148 asm volatile (
149 "mrc p15, 0, %[dummy], c5, c0, 0"
150 : [dummy] "=r" (fsu.raw)
151 );
152
153 return fsu;
154}
155
156/** Returns DFAR (fault address register) content.
157 *
158 * This register is equivalent to FAR on pre armv6 machines.
159 *
160 * @return DFAR (fault address register) content (address that caused a page
161 * fault)
162 */
163static inline uintptr_t read_data_fault_address_register(void)
164{
165 uintptr_t ret;
166
167 /* fault adress is stored in CP15 register 6 */
168 asm volatile (
169 "mrc p15, 0, %[ret], c6, c0, 0"
170 : [ret] "=r" (ret)
171 );
172
173 return ret;
174}
175
176#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
177/** Decides whether read or write into memory is requested.
178 *
179 * @param instr_addr Address of instruction which tries to access memory.
180 * @param badvaddr Virtual address the instruction tries to access.
181 *
182 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
183 * requested.
184 */
185static pf_access_t get_memory_access_type(uint32_t instr_addr,
186 uintptr_t badvaddr)
187{
188 instruction_union_t instr_union;
189 instr_union.pc = instr_addr;
190
191 instruction_t instr = *(instr_union.instr);
192
193 /* undefined instructions */
194 if (instr.condition == 0xf) {
195 panic("page_fault - instruction does not access memory "
196 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
197 *(uint32_t*)instr_union.instr, (void *) badvaddr);
198 return PF_ACCESS_EXEC;
199 }
200
201 /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
202 * A5.3 (PDF p. 206) */
203 static const struct {
204 uint32_t mask;
205 uint32_t value;
206 pf_access_t access;
207 } ls_inst[] = {
208 /* Store word/byte */
209 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /*STR(B) imm*/
210 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /*STR(B) reg*/
211 /* Load word/byte */
212 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /*LDR(B) imm*/
213 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /*LDR(B) reg*/
214 /* Store half-word/dual A5.2.8 */
215 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/
216 /* Load half-word/dual A5.2.8 */
217 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/
218 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/
219 /* Block data transfer, Store */
220 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */
221 { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */
222 /* Swap */
223 { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
224 };
225 const uint32_t inst = *(uint32_t*)instr_addr;
226 for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
227 if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
228 return ls_inst[i].access;
229 }
230 }
231
232 panic("page_fault - instruction doesn't access memory "
233 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
234 inst, (void *) badvaddr);
235}
236#endif
237
238/** Handles "data abort" exception (load or store at invalid address).
239 *
240 * @param exc_no Exception number.
241 * @param istate CPU state when exception occured.
242 *
243 */
244void data_abort(unsigned int exc_no, istate_t *istate)
245{
246 const uintptr_t badvaddr = read_data_fault_address_register();
247 const fault_status_t fsr = read_data_fault_status_register();
248 const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
249
250 switch (source) {
251 case DFSR_SOURCE_TRANSLATION_L1:
252 case DFSR_SOURCE_TRANSLATION_L2:
253 case DFSR_SOURCE_PERMISSION_L1:
254 case DFSR_SOURCE_PERMISSION_L2:
255 /* Page fault is handled further down */
256 break;
257 case DFSR_SOURCE_ALIGN:
258 case DFSR_SOURCE_CACHE_MAINTENANCE:
259 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
260 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
261 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
262 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
263 case DFSR_SOURCE_ACCESS_FLAG_L1:
264 case DFSR_SOURCE_ACCESS_FLAG_L2:
265 case DFSR_SOURCE_DOMAIN_L1:
266 case DFSR_SOURCE_DOMAIN_L2:
267 case DFSR_SOURCE_DEBUG:
268 case DFSR_SOURCE_SYNC_EXTERNAL:
269 case DFSR_SOURCE_TLB_CONFLICT:
270 case DFSR_SOURCE_LOCKDOWN:
271 case DFSR_SOURCE_COPROCESSOR:
272 case DFSR_SOURCE_SYNC_PARITY:
273 case DFSR_SOURCE_ASYNC_EXTERNAL:
274 case DFSR_SOURCE_ASYNC_PARITY:
275 case DFSR_SOURCE_MASK:
276 /* Weird abort stuff */
277 fault_if_from_uspace(istate, "Unhandled abort %s at address: "
278 "%#x.", dfsr_source_to_str(source), badvaddr);
279 panic("Unhandled abort %s at address: %#x.",
280 dfsr_source_to_str(source), badvaddr);
281 }
282
283#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
284 const pf_access_t access =
285 fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
286#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
287 const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
288#else
289#error "Unsupported architecture"
290#endif
291 const int ret = as_page_fault(badvaddr, access, istate);
292
293 if (ret == AS_PF_FAULT) {
294 fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
295 panic_memtrap(istate, access, badvaddr, NULL);
296 }
297}
298
299/** Handles "prefetch abort" exception (instruction couldn't be executed).
300 *
301 * @param exc_no Exception number.
302 * @param istate CPU state when exception occured.
303 *
304 */
305void prefetch_abort(unsigned int exc_no, istate_t *istate)
306{
307 /* NOTE: We should use IFAR and IFSR here. */
308 int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
309
310 if (ret == AS_PF_FAULT) {
311 fault_if_from_uspace(istate,
312 "Page fault - prefetch_abort: %#x.", istate->pc);
313 panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, NULL);
314 }
315}
316
317/** @}
318 */
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