source: mainline/kernel/arch/arm32/src/mm/page_fault.c@ 09ab0a9a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 09ab0a9a was 09ab0a9a, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix vertical spacing with new Ccheck revision.
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1/*
2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32mm
30 * @{
31 */
32/** @file
33 * @brief Page fault related functions.
34 */
35#include <panic.h>
36#include <arch/cp15.h>
37#include <arch/exception.h>
38#include <arch/mm/page_fault.h>
39#include <mm/as.h>
40#include <genarch/mm/page_pt.h>
41#include <arch.h>
42#include <interrupt.h>
43#include <print.h>
44
45/**
46 * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
47 *
48 * B3.13.3 page B3-1406 (PDF page 1406)
49 */
50typedef enum {
51 DFSR_SOURCE_ALIGN = 0x0001,
52 DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
53 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
54 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
55 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
56 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
57 DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
58 DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
59 DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */
60 DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
61 DFSR_SOURCE_DOMAIN_L1 = 0x0009,
62 DFSR_SOURCE_DOMAIN_L2 = 0x000b,
63 DFSR_SOURCE_PERMISSION_L1 = 0x000d,
64 DFSR_SOURCE_PERMISSION_L2 = 0x000f,
65 DFSR_SOURCE_DEBUG = 0x0002,
66 DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
67 DFSR_SOURCE_TLB_CONFLICT = 0x0400,
68 DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
69 DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
70 DFSR_SOURCE_SYNC_PARITY = 0x0409,
71 DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
72 DFSR_SOURCE_ASYNC_PARITY = 0x0408,
73 DFSR_SOURCE_MASK = 0x0000040f,
74} dfsr_source_t;
75
76static inline const char *dfsr_source_to_str(dfsr_source_t source)
77{
78 switch (source) {
79 case DFSR_SOURCE_TRANSLATION_L1:
80 return "Translation fault L1";
81 case DFSR_SOURCE_TRANSLATION_L2:
82 return "Translation fault L2";
83 case DFSR_SOURCE_PERMISSION_L1:
84 return "Permission fault L1";
85 case DFSR_SOURCE_PERMISSION_L2:
86 return "Permission fault L2";
87 case DFSR_SOURCE_ALIGN:
88 return "Alignment fault";
89 case DFSR_SOURCE_CACHE_MAINTENANCE:
90 return "Instruction cache maintenance fault";
91 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
92 return "Synchronous external abort on translation table walk level 1";
93 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
94 return "Synchronous external abort on translation table walk level 2";
95 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
96 return "Synchronous parity error on translation table walk level 1";
97 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
98 return "Synchronous parity error on translation table walk level 2";
99 case DFSR_SOURCE_ACCESS_FLAG_L1:
100 return "Access flag fault L1";
101 case DFSR_SOURCE_ACCESS_FLAG_L2:
102 return "Access flag fault L2";
103 case DFSR_SOURCE_DOMAIN_L1:
104 return "Domain fault L1";
105 case DFSR_SOURCE_DOMAIN_L2:
106 return "Domain flault L2";
107 case DFSR_SOURCE_DEBUG:
108 return "Debug event";
109 case DFSR_SOURCE_SYNC_EXTERNAL:
110 return "Synchronous external abort";
111 case DFSR_SOURCE_TLB_CONFLICT:
112 return "TLB conflict abort";
113 case DFSR_SOURCE_LOCKDOWN:
114 return "Lockdown (Implementation defined)";
115 case DFSR_SOURCE_COPROCESSOR:
116 return "Coprocessor abort (Implementation defined)";
117 case DFSR_SOURCE_SYNC_PARITY:
118 return "Synchronous parity error on memory access";
119 case DFSR_SOURCE_ASYNC_EXTERNAL:
120 return "Asynchronous external abort";
121 case DFSR_SOURCE_ASYNC_PARITY:
122 return "Asynchronous parity error on memory access";
123 case DFSR_SOURCE_MASK:
124 break;
125 }
126 return "Unknown data abort";
127}
128
129#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
130/** Decides whether read or write into memory is requested.
131 *
132 * @param instr_addr Address of instruction which tries to access memory.
133 * @param badvaddr Virtual address the instruction tries to access.
134 *
135 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
136 * requested.
137 */
138static pf_access_t get_memory_access_type(uint32_t instr_addr,
139 uintptr_t badvaddr)
140{
141 instruction_union_t instr_union;
142 instr_union.pc = instr_addr;
143
144 instruction_t instr = *(instr_union.instr);
145
146 /* undefined instructions */
147 if (instr.condition == 0xf) {
148 panic("page_fault - instruction does not access memory "
149 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
150 *(uint32_t *)instr_union.instr, (void *) badvaddr);
151 return PF_ACCESS_EXEC;
152 }
153
154 /*
155 * See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
156 * A5.3 (PDF p. 206)
157 */
158 static const struct {
159 uint32_t mask;
160 uint32_t value;
161 pf_access_t access;
162 } ls_inst[] = {
163 /* Store word/byte */
164 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /*STR(B) imm*/
165 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /*STR(B) reg*/
166 /* Load word/byte */
167 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /*LDR(B) imm*/
168 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /*LDR(B) reg*/
169 /* Store half-word/dual A5.2.8 */
170 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/
171 /* Load half-word/dual A5.2.8 */
172 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/
173 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/
174 /* Block data transfer, Store */
175 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */
176 { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */
177 /* Swap */
178 { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
179 };
180 const uint32_t inst = *(uint32_t *)instr_addr;
181 for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
182 if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
183 return ls_inst[i].access;
184 }
185 }
186
187 panic("page_fault - instruction doesn't access memory "
188 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
189 inst, (void *) badvaddr);
190}
191#endif
192
193/** Handles "data abort" exception (load or store at invalid address).
194 *
195 * @param exc_no Exception number.
196 * @param istate CPU state when exception occured.
197 *
198 */
199void data_abort(unsigned int exc_no, istate_t *istate)
200{
201 const uintptr_t badvaddr = DFAR_read();
202 const fault_status_t fsr = { .raw = DFSR_read() };
203 const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
204
205 switch (source) {
206 case DFSR_SOURCE_TRANSLATION_L1:
207 case DFSR_SOURCE_TRANSLATION_L2:
208 case DFSR_SOURCE_PERMISSION_L1:
209 case DFSR_SOURCE_PERMISSION_L2:
210 /* Page fault is handled further down */
211 break;
212 case DFSR_SOURCE_ALIGN:
213 case DFSR_SOURCE_CACHE_MAINTENANCE:
214 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
215 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
216 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
217 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
218 case DFSR_SOURCE_ACCESS_FLAG_L1:
219 case DFSR_SOURCE_ACCESS_FLAG_L2:
220 case DFSR_SOURCE_DOMAIN_L1:
221 case DFSR_SOURCE_DOMAIN_L2:
222 case DFSR_SOURCE_DEBUG:
223 case DFSR_SOURCE_SYNC_EXTERNAL:
224 case DFSR_SOURCE_TLB_CONFLICT:
225 case DFSR_SOURCE_LOCKDOWN:
226 case DFSR_SOURCE_COPROCESSOR:
227 case DFSR_SOURCE_SYNC_PARITY:
228 case DFSR_SOURCE_ASYNC_EXTERNAL:
229 case DFSR_SOURCE_ASYNC_PARITY:
230 case DFSR_SOURCE_MASK:
231 /* Weird abort stuff */
232 fault_if_from_uspace(istate, "Unhandled abort %s at address: "
233 "%#x.", dfsr_source_to_str(source), badvaddr);
234 panic("Unhandled abort %s at address: %#x.",
235 dfsr_source_to_str(source), badvaddr);
236 }
237
238#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
239 const pf_access_t access =
240 fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
241#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
242 const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
243#else
244#error "Unsupported architecture"
245#endif
246 as_page_fault(badvaddr, access, istate);
247}
248
249/** Handles "prefetch abort" exception (instruction couldn't be executed).
250 *
251 * @param exc_no Exception number.
252 * @param istate CPU state when exception occured.
253 *
254 */
255void prefetch_abort(unsigned int exc_no, istate_t *istate)
256{
257 as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
258}
259
260/** @}
261 */
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