source: mainline/kernel/arch/arm32/src/mm/page_fault.c@ 999efa9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 999efa9 was 999efa9, checked in by Jakub Jermar <jakub@…>, 8 years ago

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[6b781c0]1/*
[999efa9]2 * Copyright (c) 2007 Pavel Jancik
3 * Copyright (c) 2007 Michal Kebrt
[6b781c0]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup arm32mm
31 * @{
32 */
33/** @file
34 * @brief Page fault related functions.
35 */
36#include <panic.h>
[612edca]37#include <arch/cp15.h>
[6b781c0]38#include <arch/exception.h>
39#include <arch/mm/page_fault.h>
40#include <mm/as.h>
41#include <genarch/mm/page_pt.h>
42#include <arch.h>
43#include <interrupt.h>
[009474f]44#include <print.h>
[6b781c0]45
[25d5c96]46
47/**
48 * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
49 *
50 * B3.13.3 page B3-1406 (PDF page 1406)
51 */
52typedef enum {
53 DFSR_SOURCE_ALIGN = 0x0001,
54 DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
55 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
56 DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
57 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
58 DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
59 DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
60 DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
61 DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */
62 DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
63 DFSR_SOURCE_DOMAIN_L1 = 0x0009,
64 DFSR_SOURCE_DOMAIN_L2 = 0x000b,
65 DFSR_SOURCE_PERMISSION_L1 = 0x000d,
66 DFSR_SOURCE_PERMISSION_L2 = 0x000f,
67 DFSR_SOURCE_DEBUG = 0x0002,
68 DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
69 DFSR_SOURCE_TLB_CONFLICT = 0x0400,
70 DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
71 DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
72 DFSR_SOURCE_SYNC_PARITY = 0x0409,
73 DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
74 DFSR_SOURCE_ASYNC_PARITY = 0x0408,
75 DFSR_SOURCE_MASK = 0x0000040f,
76} dfsr_source_t;
77
78static inline const char * dfsr_source_to_str(dfsr_source_t source)
79{
[9e96666]80 switch (source) {
[25d5c96]81 case DFSR_SOURCE_TRANSLATION_L1:
82 return "Translation fault L1";
83 case DFSR_SOURCE_TRANSLATION_L2:
84 return "Translation fault L2";
85 case DFSR_SOURCE_PERMISSION_L1:
86 return "Permission fault L1";
87 case DFSR_SOURCE_PERMISSION_L2:
88 return "Permission fault L2";
89 case DFSR_SOURCE_ALIGN:
90 return "Alignment fault";
91 case DFSR_SOURCE_CACHE_MAINTENANCE:
92 return "Instruction cache maintenance fault";
93 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
94 return "Synchronous external abort on translation table walk level 1";
95 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
96 return "Synchronous external abort on translation table walk level 2";
97 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
98 return "Synchronous parity error on translation table walk level 1";
99 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
100 return "Synchronous parity error on translation table walk level 2";
101 case DFSR_SOURCE_ACCESS_FLAG_L1:
102 return "Access flag fault L1";
103 case DFSR_SOURCE_ACCESS_FLAG_L2:
104 return "Access flag fault L2";
105 case DFSR_SOURCE_DOMAIN_L1:
106 return "Domain fault L1";
107 case DFSR_SOURCE_DOMAIN_L2:
108 return "Domain flault L2";
109 case DFSR_SOURCE_DEBUG:
110 return "Debug event";
111 case DFSR_SOURCE_SYNC_EXTERNAL:
112 return "Synchronous external abort";
113 case DFSR_SOURCE_TLB_CONFLICT:
114 return "TLB conflict abort";
115 case DFSR_SOURCE_LOCKDOWN:
116 return "Lockdown (Implementation defined)";
117 case DFSR_SOURCE_COPROCESSOR:
118 return "Coprocessor abort (Implementation defined)";
119 case DFSR_SOURCE_SYNC_PARITY:
120 return "Synchronous parity error on memory access";
121 case DFSR_SOURCE_ASYNC_EXTERNAL:
122 return "Asynchronous external abort";
123 case DFSR_SOURCE_ASYNC_PARITY:
124 return "Asynchronous parity error on memory access";
125 case DFSR_SOURCE_MASK:
126 break;
127 }
128 return "Unknown data abort";
129}
130
[5d9e36b]131#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
[6b781c0]132/** Decides whether read or write into memory is requested.
133 *
134 * @param instr_addr Address of instruction which tries to access memory.
135 * @param badvaddr Virtual address the instruction tries to access.
136 *
137 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
[60d931d]138 * requested.
[6b781c0]139 */
140static pf_access_t get_memory_access_type(uint32_t instr_addr,
141 uintptr_t badvaddr)
142{
143 instruction_union_t instr_union;
144 instr_union.pc = instr_addr;
145
146 instruction_t instr = *(instr_union.instr);
147
148 /* undefined instructions */
149 if (instr.condition == 0xf) {
[f651e80]150 panic("page_fault - instruction does not access memory "
[7e752b2]151 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
[774c143]152 *(uint32_t*)instr_union.instr, (void *) badvaddr);
[6b781c0]153 return PF_ACCESS_EXEC;
154 }
155
[2ddb3c5]156 /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
157 * A5.3 (PDF p. 206) */
158 static const struct {
159 uint32_t mask;
160 uint32_t value;
161 pf_access_t access;
162 } ls_inst[] = {
[d126d3e]163 /* Store word/byte */
164 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /*STR(B) imm*/
165 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /*STR(B) reg*/
166 /* Load word/byte */
[1ef7fb2]167 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /*LDR(B) imm*/
168 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /*LDR(B) reg*/
[2ddb3c5]169 /* Store half-word/dual A5.2.8 */
[bbb0a400]170 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/
[2ddb3c5]171 /* Load half-word/dual A5.2.8 */
172 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/
[bbb0a400]173 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/
[2ddb3c5]174 /* Block data transfer, Store */
175 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */
176 { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */
[f13f5d60]177 /* Swap */
178 { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
[2ddb3c5]179 };
[60d931d]180 const uint32_t inst = *(uint32_t*)instr_addr;
[2ddb3c5]181 for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
182 if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
[87e5b526]183 return ls_inst[i].access;
[6b781c0]184 }
185 }
186
187 panic("page_fault - instruction doesn't access memory "
[7e752b2]188 "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
[60d931d]189 inst, (void *) badvaddr);
[6b781c0]190}
[ecd1a0a]191#endif
[6b781c0]192
193/** Handles "data abort" exception (load or store at invalid address).
194 *
[214ec25c]195 * @param exc_no Exception number.
196 * @param istate CPU state when exception occured.
197 *
[6b781c0]198 */
[214ec25c]199void data_abort(unsigned int exc_no, istate_t *istate)
[6b781c0]200{
[612edca]201 const uintptr_t badvaddr = DFAR_read();
202 const fault_status_t fsr = { .raw = DFSR_read() };
[25d5c96]203 const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
204
[9e96666]205 switch (source) {
[25d5c96]206 case DFSR_SOURCE_TRANSLATION_L1:
207 case DFSR_SOURCE_TRANSLATION_L2:
208 case DFSR_SOURCE_PERMISSION_L1:
209 case DFSR_SOURCE_PERMISSION_L2:
210 /* Page fault is handled further down */
211 break;
212 case DFSR_SOURCE_ALIGN:
213 case DFSR_SOURCE_CACHE_MAINTENANCE:
214 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
215 case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
216 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
217 case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
218 case DFSR_SOURCE_ACCESS_FLAG_L1:
219 case DFSR_SOURCE_ACCESS_FLAG_L2:
220 case DFSR_SOURCE_DOMAIN_L1:
221 case DFSR_SOURCE_DOMAIN_L2:
222 case DFSR_SOURCE_DEBUG:
223 case DFSR_SOURCE_SYNC_EXTERNAL:
224 case DFSR_SOURCE_TLB_CONFLICT:
225 case DFSR_SOURCE_LOCKDOWN:
226 case DFSR_SOURCE_COPROCESSOR:
227 case DFSR_SOURCE_SYNC_PARITY:
228 case DFSR_SOURCE_ASYNC_EXTERNAL:
229 case DFSR_SOURCE_ASYNC_PARITY:
230 case DFSR_SOURCE_MASK:
231 /* Weird abort stuff */
232 fault_if_from_uspace(istate, "Unhandled abort %s at address: "
233 "%#x.", dfsr_source_to_str(source), badvaddr);
234 panic("Unhandled abort %s at address: %#x.",
235 dfsr_source_to_str(source), badvaddr);
236 }
[ecd1a0a]237
[5d9e36b]238#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
[ecd1a0a]239 const pf_access_t access =
240 fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
[5d9e36b]241#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
[ecd1a0a]242 const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
243#else
244#error "Unsupported architecture"
245#endif
[1dbc43f]246 as_page_fault(badvaddr, access, istate);
[6b781c0]247}
248
249/** Handles "prefetch abort" exception (instruction couldn't be executed).
250 *
[214ec25c]251 * @param exc_no Exception number.
252 * @param istate CPU state when exception occured.
253 *
[6b781c0]254 */
[214ec25c]255void prefetch_abort(unsigned int exc_no, istate_t *istate)
[6b781c0]256{
[1dbc43f]257 as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
[6b781c0]258}
259
260/** @}
261 */
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