[7c866dc] | 1 | /*
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| 2 | * Copyright (c) 2010 Jiri Svoboda
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_arm32_gta02
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[7c866dc] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Openmoko GTA02 (Neo FreeRunner) platform driver.
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| 34 | */
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| 35 |
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| 36 | #include <arch/exception.h>
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| 37 | #include <arch/mach/gta02/gta02.h>
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[d7ef14b] | 38 | #include <arch/mm/page.h>
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[f1fc83a] | 39 | #include <mm/page.h>
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[d4673296] | 40 | #include <mm/km.h>
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[5c032932] | 41 | #include <genarch/fb/fb.h>
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[c0699467] | 42 | #include <abi/fb/visuals.h>
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[96b9724] | 43 | #include <genarch/drivers/s3c24xx/uart.h>
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| 44 | #include <genarch/drivers/s3c24xx/irqc.h>
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| 45 | #include <genarch/drivers/s3c24xx/timer.h>
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[ec08286] | 46 | #include <genarch/srln/srln.h>
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[a9b5b5f] | 47 | #include <sysinfo/sysinfo.h>
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[41ce4d9] | 48 | #include <interrupt.h>
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[5c032932] | 49 | #include <ddi/ddi.h>
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[b2fa1204] | 50 | #include <log.h>
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[d7ef14b] | 51 |
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| 52 | #define GTA02_MEMORY_START 0x30000000 /* physical */
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| 53 | #define GTA02_MEMORY_SIZE 0x08000000 /* 128 MB */
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[f1fc83a] | 54 | #define GTA02_MEMORY_SKIP 0x8000
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| 55 |
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| 56 | /** GTA02 serial console UART address (UART S3C24XX CPU UART channel 2). */
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| 57 | #define GTA02_SCONS_BASE 0x50008000
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[7c866dc] | 58 |
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[5c032932] | 59 | /** GTA02 framebuffer base address */
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| 60 | #define GTA02_FB_BASE 0x08800000
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| 61 |
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[41ce4d9] | 62 | /** IRQ number used for clock */
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| 63 | #define GTA02_TIMER_IRQ S3C24XX_INT_TIMER0
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| 64 |
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[7c866dc] | 65 | static void gta02_init(void);
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| 66 | static void gta02_timer_irq_start(void);
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| 67 | static void gta02_cpu_halt(void);
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[2686705] | 68 | static void gta02_get_memory_extents(uintptr_t *start, size_t *size);
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[7c866dc] | 69 | static void gta02_irq_exception(unsigned int exc_no, istate_t *istate);
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| 70 | static void gta02_frame_init(void);
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| 71 | static void gta02_output_init(void);
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| 72 | static void gta02_input_init(void);
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[ecf083dd] | 73 | static size_t gta02_get_irq_count(void);
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[eff1f033] | 74 | static const char *gta02_get_platform_name(void);
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[7c866dc] | 75 |
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[41ce4d9] | 76 | static void gta02_timer_irq_init(void);
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| 77 | static void gta02_timer_start(void);
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| 78 | static irq_ownership_t gta02_timer_irq_claim(irq_t *irq);
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| 79 | static void gta02_timer_irq_handler(irq_t *irq);
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| 80 |
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[ec08286] | 81 | static outdev_t *gta02_scons_dev;
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| 82 | static s3c24xx_irqc_t gta02_irqc;
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[41ce4d9] | 83 | static s3c24xx_timer_t *gta02_timer;
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| 84 |
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| 85 | static irq_t gta02_timer_irq;
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[f1fc83a] | 86 |
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[7c866dc] | 87 | struct arm_machine_ops gta02_machine_ops = {
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| 88 | gta02_init,
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| 89 | gta02_timer_irq_start,
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| 90 | gta02_cpu_halt,
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[d7ef14b] | 91 | gta02_get_memory_extents,
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[7c866dc] | 92 | gta02_irq_exception,
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| 93 | gta02_frame_init,
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| 94 | gta02_output_init,
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[ecf083dd] | 95 | gta02_input_init,
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[eff1f033] | 96 | gta02_get_irq_count,
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| 97 | gta02_get_platform_name
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[7c866dc] | 98 | };
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| 99 |
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| 100 | static void gta02_init(void)
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| 101 | {
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[ec08286] | 102 | s3c24xx_irqc_regs_t *irqc_regs;
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| 103 |
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[adec5b45] | 104 | gta02_timer = (void *) km_map(S3C24XX_TIMER_ADDRESS, PAGE_SIZE,
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[a1b9f63] | 105 | PAGE_SIZE, PAGE_NOT_CACHEABLE);
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| 106 | irqc_regs = (void *) km_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE, PAGE_SIZE,
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[adec5b45] | 107 | PAGE_NOT_CACHEABLE);
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[41ce4d9] | 108 |
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[ec08286] | 109 | /* Initialize interrupt controller. */
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| 110 | s3c24xx_irqc_init(>a02_irqc, irqc_regs);
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[7c866dc] | 111 | }
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| 112 |
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| 113 | static void gta02_timer_irq_start(void)
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| 114 | {
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[41ce4d9] | 115 | gta02_timer_irq_init();
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| 116 | gta02_timer_start();
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[7c866dc] | 117 | }
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| 118 |
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| 119 | static void gta02_cpu_halt(void)
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| 120 | {
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| 121 | }
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| 122 |
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[d7ef14b] | 123 | /** Get extents of available memory.
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| 124 | *
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[6250c37] | 125 | * @param start Place to store memory start address (physical).
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[d7ef14b] | 126 | * @param size Place to store memory size.
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| 127 | */
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[2686705] | 128 | static void gta02_get_memory_extents(uintptr_t *start, size_t *size)
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[7c866dc] | 129 | {
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[6250c37] | 130 | *start = GTA02_MEMORY_START + GTA02_MEMORY_SKIP;
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[d7ef14b] | 131 | *size = GTA02_MEMORY_SIZE - GTA02_MEMORY_SKIP;
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[7c866dc] | 132 | }
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| 133 |
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| 134 | static void gta02_irq_exception(unsigned int exc_no, istate_t *istate)
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| 135 | {
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[41ce4d9] | 136 | uint32_t inum;
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| 137 |
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[ec08286] | 138 | /* Determine IRQ number. */
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| 139 | inum = s3c24xx_irqc_inum_get(>a02_irqc);
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| 140 |
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| 141 | /* Clear interrupt condition in the interrupt controller. */
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| 142 | s3c24xx_irqc_clear(>a02_irqc, inum);
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[41ce4d9] | 143 |
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| 144 | irq_t *irq = irq_dispatch_and_lock(inum);
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| 145 | if (irq) {
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| 146 | /* The IRQ handler was found. */
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| 147 | irq->handler(irq);
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[b67ce1ff] | 148 | irq_spinlock_unlock(&irq->lock, false);
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[41ce4d9] | 149 | } else {
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[d1582b50] | 150 | /* Spurious interrupt. */
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[b2fa1204] | 151 | log(LF_ARCH, LVL_DEBUG, "cpu%d: spurious interrupt (inum=%d)",
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[41ce4d9] | 152 | CPU->id, inum);
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| 153 | }
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[7c866dc] | 154 | }
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| 155 |
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| 156 | static void gta02_frame_init(void)
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| 157 | {
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| 158 | }
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| 159 |
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| 160 | static void gta02_output_init(void)
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| 161 | {
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[5c032932] | 162 | #ifdef CONFIG_FB
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| 163 | fb_properties_t prop = {
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| 164 | .addr = GTA02_FB_BASE,
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| 165 | .offset = 0,
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| 166 | .x = 480,
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| 167 | .y = 640,
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| 168 | .scan = 960,
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| 169 | .visual = VISUAL_RGB_5_6_5_LE
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| 170 | };
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| 171 |
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| 172 | outdev_t *fb_dev = fb_init(&prop);
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[b366a6f4] | 173 | if (fb_dev)
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[5c032932] | 174 | stdout_wire(fb_dev);
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| 175 | #endif
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[f1fc83a] | 176 |
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[ec08286] | 177 | /* Initialize serial port of the debugging console. */
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[b366a6f4] | 178 | gta02_scons_dev =
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| 179 | s3c24xx_uart_init(GTA02_SCONS_BASE, S3C24XX_INT_UART2);
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[ec08286] | 180 |
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[277cf60] | 181 | if (gta02_scons_dev) {
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[ec08286] | 182 | /* Create output device. */
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| 183 | stdout_wire(gta02_scons_dev);
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| 184 | }
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[a9b5b5f] | 185 |
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| 186 | /*
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| 187 | * This is the necessary evil until the userspace driver is entirely
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| 188 | * self-sufficient.
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| 189 | */
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| 190 | sysinfo_set_item_val("s3c24xx_uart", NULL, true);
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| 191 | sysinfo_set_item_val("s3c24xx_uart.inr", NULL, S3C24XX_INT_UART2);
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| 192 | sysinfo_set_item_val("s3c24xx_uart.address.physical", NULL,
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| 193 | (uintptr_t) GTA02_SCONS_BASE);
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| 194 |
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[7c866dc] | 195 | }
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| 196 |
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| 197 | static void gta02_input_init(void)
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| 198 | {
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[277cf60] | 199 | s3c24xx_uart_t *scons_inst;
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[ec08286] | 200 |
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| 201 | if (gta02_scons_dev) {
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| 202 | /* Create input device. */
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| 203 | scons_inst = (void *) gta02_scons_dev->data;
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| 204 |
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| 205 | srln_instance_t *srln_instance = srln_init();
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| 206 | if (srln_instance) {
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| 207 | indev_t *sink = stdin_wire();
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| 208 | indev_t *srln = srln_wire(srln_instance, sink);
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| 209 | s3c24xx_uart_input_wire(scons_inst, srln);
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| 210 |
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| 211 | /* Enable interrupts from UART2 */
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| 212 | s3c24xx_irqc_src_enable(>a02_irqc,
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| 213 | S3C24XX_INT_UART2);
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| 214 |
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| 215 | /* Enable interrupts from UART2 RXD */
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| 216 | s3c24xx_irqc_subsrc_enable(>a02_irqc,
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| 217 | S3C24XX_SUBINT_RXD2);
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| 218 | }
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| 219 | }
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[527298a] | 220 |
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| 221 | /* Enable interrupts from ADC */
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| 222 | s3c24xx_irqc_src_enable(>a02_irqc, S3C24XX_INT_ADC);
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| 223 |
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| 224 | /* Enable interrupts from ADC sub-sources */
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| 225 | s3c24xx_irqc_subsrc_enable(>a02_irqc, S3C24XX_SUBINT_ADC_S);
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| 226 | s3c24xx_irqc_subsrc_enable(>a02_irqc, S3C24XX_SUBINT_TC);
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[7c866dc] | 227 | }
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| 228 |
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[ecf083dd] | 229 | size_t gta02_get_irq_count(void)
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| 230 | {
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| 231 | return GTA02_IRQ_COUNT;
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| 232 | }
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| 233 |
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[eff1f033] | 234 | const char *gta02_get_platform_name(void)
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| 235 | {
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| 236 | return "gta02";
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| 237 | }
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| 238 |
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[41ce4d9] | 239 | static void gta02_timer_irq_init(void)
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| 240 | {
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| 241 | irq_initialize(>a02_timer_irq);
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| 242 | gta02_timer_irq.inr = GTA02_TIMER_IRQ;
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| 243 | gta02_timer_irq.claim = gta02_timer_irq_claim;
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| 244 | gta02_timer_irq.handler = gta02_timer_irq_handler;
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| 245 |
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| 246 | irq_register(>a02_timer_irq);
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| 247 | }
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| 248 |
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| 249 | static irq_ownership_t gta02_timer_irq_claim(irq_t *irq)
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| 250 | {
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| 251 | return IRQ_ACCEPT;
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| 252 | }
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| 253 |
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| 254 | static void gta02_timer_irq_handler(irq_t *irq)
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| 255 | {
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| 256 | /*
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| 257 | * We are holding a lock which prevents preemption.
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| 258 | * Release the lock, call clock() and reacquire the lock again.
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| 259 | */
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[b67ce1ff] | 260 | irq_spinlock_unlock(&irq->lock, false);
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[41ce4d9] | 261 | clock();
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[b67ce1ff] | 262 | irq_spinlock_lock(&irq->lock, false);
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[41ce4d9] | 263 | }
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| 264 |
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| 265 | static void gta02_timer_start(void)
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| 266 | {
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| 267 | s3c24xx_timer_t *timer = gta02_timer;
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| 268 |
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| 269 | /*
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| 270 | * See S3C2442B user manual chapter 10 (PWM Timer) for description
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| 271 | * of timer operation. Starting a timer is described in the
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| 272 | * section 'Timer initialization using manual update bit and
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| 273 | * inverter bit'.
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| 274 | */
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| 275 |
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[24697c3] | 276 | /*
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| 277 | * GTA02 PCLK should be 100 MHz.
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| 278 | * Timer input freq. = PCLK / divider / (1+prescaler)
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| 279 | * 100 MHz / 2 / (1+7) / 62500 ~= 100 Hz
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| 280 | */
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| 281 | #if HZ != 100
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| 282 | #warning Other HZ than 100 not suppored.
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| 283 | #endif
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| 284 |
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| 285 | /* Set prescaler values. No pre-divison, no dead zone. */
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| 286 | pio_write_32(&timer->tcfg0, 7); /* prescale 1/8 */
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[41ce4d9] | 287 |
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| 288 | /* No DMA request, divider value = 2 for all timers. */
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| 289 | pio_write_32(&timer->tcfg1, 0);
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| 290 |
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| 291 | /* Stop all timers. */
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| 292 | pio_write_32(&timer->tcon, 0);
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| 293 |
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| 294 | /* Start counting from 64k-1. Compare value is irrelevant. */
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[24697c3] | 295 | pio_write_32(&timer->timer[0].cntb, 62500);
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[41ce4d9] | 296 | pio_write_32(&timer->timer[0].cmpb, 0);
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| 297 |
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| 298 | /* Enable interrupts from timer0 */
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[ec08286] | 299 | s3c24xx_irqc_src_enable(>a02_irqc, S3C24XX_INT_TIMER0);
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[41ce4d9] | 300 |
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| 301 | /* Load data from tcntb0/tcmpb0 into tcnt0/tcmp0. */
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| 302 | pio_write_32(&timer->tcon, TCON_T0_AUTO_RLD | TCON_T0_MUPDATE);
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| 303 |
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| 304 | /* Start timer 0. Inverter is off. */
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| 305 | pio_write_32(&timer->tcon, TCON_T0_AUTO_RLD | TCON_T0_START);
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| 306 | }
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| 307 |
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[7c866dc] | 308 | /** @}
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| 309 | */
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