[dcb0751] | 1 | /*
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| 2 | * Copyright (c) 2012 Adam Hraska
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup arm32
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Atomic operations emulation.
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| 34 | */
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| 35 |
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| 36 | #include <synch/spinlock.h>
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| 37 |
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| 38 |
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| 39 | IRQ_SPINLOCK_STATIC_INITIALIZE_NAME(cas_lock, "arm-cas-lock");
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| 40 |
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| 41 | /** Implements GCC's missing compare-and-swap intrinsic for ARM.
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| 42 | *
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| 43 | * Sets \a *ptr to \a new_val if it is equal to \a expected. In any case,
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| 44 | * returns the previous value of \a *ptr.
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| 45 | */
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[1433ecda] | 46 | void *__sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
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[dcb0751] | 47 | {
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[1b20da0] | 48 | /*
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[dcb0751] | 49 | * Using an interrupt disabling spinlock might still lead to deadlock
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| 50 | * if CAS() is used in an exception handler. Eg. if a CAS() results
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| 51 | * in a page fault exception and the exception handler again tries
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| 52 | * to invoke CAS() (even for a different memory location), the spinlock
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| 53 | * would deadlock.
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| 54 | */
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| 55 | irq_spinlock_lock(&cas_lock, true);
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[a35b458] | 56 |
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[1433ecda] | 57 | void *cur_val = *ptr;
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[a35b458] | 58 |
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[dcb0751] | 59 | if (cur_val == expected) {
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| 60 | *ptr = new_val;
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| 61 | }
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[a35b458] | 62 |
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[dcb0751] | 63 | irq_spinlock_unlock(&cas_lock, true);
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[a35b458] | 64 |
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[dcb0751] | 65 | return cur_val;
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| 66 | }
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| 67 |
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[9ce35f0] | 68 | /* Naive implementations of the newer intrinsics. */
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| 69 |
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| 70 | _Bool __atomic_compare_exchange_4(void **mem, void **expected, void *desired, _Bool weak, int success, int failure)
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| 71 | {
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| 72 | (void) weak;
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| 73 | (void) success;
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| 74 | (void) failure;
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| 75 |
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| 76 | void *old = *expected;
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| 77 | void *new = __sync_val_compare_and_swap_4(mem, old, desired);
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| 78 | if (old == new) {
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| 79 | return 1;
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| 80 | } else {
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| 81 | *expected = new;
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| 82 | return 0;
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| 83 | }
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| 84 | }
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| 85 |
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| 86 | void *__atomic_exchange_4(void **mem, void *val, int model)
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| 87 | {
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| 88 | (void) model;
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| 89 |
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| 90 | irq_spinlock_lock(&cas_lock, true);
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| 91 | void *old = *mem;
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| 92 | *mem = val;
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| 93 | irq_spinlock_unlock(&cas_lock, true);
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| 94 |
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| 95 | return old;
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| 96 | }
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[dcb0751] | 97 |
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| 98 | /** @}
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| 99 | */
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