source: mainline/kernel/arch/arm32/src/atomic.c@ 3bacee1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3bacee1 was 1433ecda, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix cstyle: make ccheck-fix and commit only files where all the changes are good.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * Copyright (c) 2012 Adam Hraska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief Atomic operations emulation.
34 */
35
36#include <synch/spinlock.h>
37
38
39IRQ_SPINLOCK_STATIC_INITIALIZE_NAME(cas_lock, "arm-cas-lock");
40
41/** Implements GCC's missing compare-and-swap intrinsic for ARM.
42 *
43 * Sets \a *ptr to \a new_val if it is equal to \a expected. In any case,
44 * returns the previous value of \a *ptr.
45 */
46void *__sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
47{
48 /*
49 * Using an interrupt disabling spinlock might still lead to deadlock
50 * if CAS() is used in an exception handler. Eg. if a CAS() results
51 * in a page fault exception and the exception handler again tries
52 * to invoke CAS() (even for a different memory location), the spinlock
53 * would deadlock.
54 */
55 irq_spinlock_lock(&cas_lock, true);
56
57 void *cur_val = *ptr;
58
59 if (cur_val == expected) {
60 *ptr = new_val;
61 }
62
63 irq_spinlock_unlock(&cas_lock, true);
64
65 return cur_val;
66}
67
68/* Naive implementations of the newer intrinsics. */
69
70_Bool __atomic_compare_exchange_4(void **mem, void **expected, void *desired, _Bool weak, int success, int failure)
71{
72 (void) weak;
73 (void) success;
74 (void) failure;
75
76 void *old = *expected;
77 void *new = __sync_val_compare_and_swap_4(mem, old, desired);
78 if (old == new) {
79 return 1;
80 } else {
81 *expected = new;
82 return 0;
83 }
84}
85
86void *__atomic_exchange_4(void **mem, void *val, int model)
87{
88 (void) model;
89
90 irq_spinlock_lock(&cas_lock, true);
91 void *old = *mem;
92 *mem = val;
93 irq_spinlock_unlock(&cas_lock, true);
94
95 return old;
96}
97
98/** @}
99 */
Note: See TracBrowser for help on using the repository browser.