| 1 | /*
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| 2 | * Copyright (c) 2008 Jakub Jermar
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| 3 | * Copyright (c) 2005-2006 Ondrej Palkovsky
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @addtogroup amd64
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| 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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| 36 | #include <arch.h>
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| 37 | #include <arch/pm.h>
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| 38 | #include <arch/asm.h>
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| 39 | #include <mm/as.h>
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| 40 | #include <mm/frame.h>
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| 41 | #include <memstr.h>
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| 42 | #include <mm/slab.h>
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| 43 |
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| 44 | /*
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| 45 | * There is no segmentation in long mode so we set up flat mode. In this
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| 46 | * mode, we use, for each privilege level, two segments spanning the
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| 47 | * whole memory. One is for code and one is for data.
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| 48 | */
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| 49 |
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| 50 | descriptor_t gdt[GDT_ITEMS] = {
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| 51 | /* NULL descriptor */
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| 52 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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| 53 | /* KTEXT descriptor */
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| 54 | { .limit_0_15 = 0xffffU,
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| 55 | .base_0_15 = 0,
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| 56 | .base_16_23 = 0,
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| 57 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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| 58 | .limit_16_19 = 0x0fU,
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| 59 | .available = 0,
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| 60 | .longmode = 1,
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| 61 | .special = 0,
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| 62 | .granularity = 1,
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| 63 | .base_24_31 = 0 },
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| 64 | /* KDATA descriptor */
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| 65 | { .limit_0_15 = 0xffffU,
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| 66 | .base_0_15 = 0,
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| 67 | .base_16_23 = 0,
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| 68 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
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| 69 | .limit_16_19 = 0x0fU,
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| 70 | .available = 0,
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| 71 | .longmode = 0,
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| 72 | .special = 0,
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| 73 | .granularity = 1,
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| 74 | .base_24_31 = 0 },
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| 75 | /* UDATA descriptor */
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| 76 | { .limit_0_15 = 0xffffU,
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| 77 | .base_0_15 = 0,
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| 78 | .base_16_23 = 0,
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| 79 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
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| 80 | .limit_16_19 = 0x0fU,
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| 81 | .available = 0,
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| 82 | .longmode = 0,
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| 83 | .special = 1,
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| 84 | .granularity = 1,
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| 85 | .base_24_31 = 0 },
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| 86 | /* UTEXT descriptor */
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| 87 | { .limit_0_15 = 0xffffU,
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| 88 | .base_0_15 = 0,
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| 89 | .base_16_23 = 0,
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| 90 | .access = AR_PRESENT | AR_CODE | DPL_USER,
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| 91 | .limit_16_19 = 0x0fU,
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| 92 | .available = 0,
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| 93 | .longmode = 1,
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| 94 | .special = 0,
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| 95 | .granularity = 1,
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| 96 | .base_24_31 = 0 },
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| 97 | /* KTEXT 32-bit protected, for protected mode before long mode */
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| 98 | { .limit_0_15 = 0xffffU,
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| 99 | .base_0_15 = 0,
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| 100 | .base_16_23 = 0,
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| 101 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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| 102 | .limit_16_19 = 0x0fU,
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| 103 | .available = 0,
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| 104 | .longmode = 0,
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| 105 | .special = 1,
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| 106 | .granularity = 1,
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| 107 | .base_24_31 = 0 },
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| 108 | /* TSS descriptor - set up will be completed later,
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| 109 | * on AMD64 it is 64-bit - 2 items in table */
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| 110 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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| 111 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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| 112 | /* VESA Init descriptor */
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| 113 | #ifdef CONFIG_FB
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| 114 | {
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| 115 | 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
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| 116 | 0xf, 0, 0, 0, 0, 0
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| 117 | }
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| 118 | #endif
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| 119 | };
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| 120 |
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| 121 | idescriptor_t idt[IDT_ITEMS];
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| 122 |
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| 123 | ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt };
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| 124 | ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt };
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| 125 |
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| 126 | static tss_t tss;
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| 127 | tss_t *tss_p = NULL;
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| 128 |
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| 129 | void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
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| 130 | {
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| 131 | tss_descriptor_t *td = (tss_descriptor_t *) d;
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| 132 |
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| 133 | td->base_0_15 = base & 0xffffU;
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| 134 | td->base_16_23 = ((base) >> 16) & 0xffU;
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| 135 | td->base_24_31 = ((base) >> 24) & 0xffU;
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| 136 | td->base_32_63 = ((base) >> 32);
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| 137 | }
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| 138 |
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| 139 | void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
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| 140 | {
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| 141 | tss_descriptor_t *td = (tss_descriptor_t *) d;
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| 142 |
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| 143 | td->limit_0_15 = limit & 0xffffU;
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| 144 | td->limit_16_19 = (limit >> 16) & 0x0fU;
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| 145 | }
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| 146 |
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| 147 | void idt_setoffset(idescriptor_t *d, uintptr_t offset)
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| 148 | {
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| 149 | /*
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| 150 | * Offset is a linear address.
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| 151 | */
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| 152 | d->offset_0_15 = offset & 0xffffU;
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| 153 | d->offset_16_31 = (offset >> 16) & 0xffffU;
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| 154 | d->offset_32_63 = offset >> 32;
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| 155 | }
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| 156 |
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| 157 | void tss_initialize(tss_t *t)
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| 158 | {
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| 159 | memsetb(t, sizeof(tss_t), 0);
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| 160 | }
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| 161 |
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| 162 | /*
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| 163 | * This function takes care of proper setup of IDT and IDTR.
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| 164 | */
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| 165 | void idt_init(void)
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| 166 | {
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| 167 | idescriptor_t *d;
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| 168 | unsigned int i;
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| 169 |
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| 170 | for (i = 0; i < IDT_ITEMS; i++) {
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| 171 | d = &idt[i];
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| 172 |
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| 173 | d->unused = 0;
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| 174 | d->selector = GDT_SELECTOR(KTEXT_DES);
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| 175 |
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| 176 | d->present = 1;
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| 177 | d->type = AR_INTERRUPT; /* masking interrupt */
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| 178 | }
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| 179 |
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| 180 | d = &idt[0];
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| 181 | idt_setoffset(d++, (uintptr_t) &int_0);
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| 182 | idt_setoffset(d++, (uintptr_t) &int_1);
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| 183 | idt_setoffset(d++, (uintptr_t) &int_2);
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| 184 | idt_setoffset(d++, (uintptr_t) &int_3);
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| 185 | idt_setoffset(d++, (uintptr_t) &int_4);
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| 186 | idt_setoffset(d++, (uintptr_t) &int_5);
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| 187 | idt_setoffset(d++, (uintptr_t) &int_6);
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| 188 | idt_setoffset(d++, (uintptr_t) &int_7);
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| 189 | idt_setoffset(d++, (uintptr_t) &int_8);
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| 190 | idt_setoffset(d++, (uintptr_t) &int_9);
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| 191 | idt_setoffset(d++, (uintptr_t) &int_10);
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| 192 | idt_setoffset(d++, (uintptr_t) &int_11);
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| 193 | idt_setoffset(d++, (uintptr_t) &int_12);
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| 194 | idt_setoffset(d++, (uintptr_t) &int_13);
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| 195 | idt_setoffset(d++, (uintptr_t) &int_14);
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| 196 | idt_setoffset(d++, (uintptr_t) &int_15);
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| 197 | idt_setoffset(d++, (uintptr_t) &int_16);
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| 198 | idt_setoffset(d++, (uintptr_t) &int_17);
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| 199 | idt_setoffset(d++, (uintptr_t) &int_18);
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| 200 | idt_setoffset(d++, (uintptr_t) &int_19);
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| 201 | idt_setoffset(d++, (uintptr_t) &int_20);
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| 202 | idt_setoffset(d++, (uintptr_t) &int_21);
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| 203 | idt_setoffset(d++, (uintptr_t) &int_22);
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| 204 | idt_setoffset(d++, (uintptr_t) &int_23);
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| 205 | idt_setoffset(d++, (uintptr_t) &int_24);
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| 206 | idt_setoffset(d++, (uintptr_t) &int_25);
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| 207 | idt_setoffset(d++, (uintptr_t) &int_26);
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| 208 | idt_setoffset(d++, (uintptr_t) &int_27);
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| 209 | idt_setoffset(d++, (uintptr_t) &int_28);
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| 210 | idt_setoffset(d++, (uintptr_t) &int_29);
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| 211 | idt_setoffset(d++, (uintptr_t) &int_30);
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| 212 | idt_setoffset(d++, (uintptr_t) &int_31);
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| 213 | idt_setoffset(d++, (uintptr_t) &int_32);
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| 214 | idt_setoffset(d++, (uintptr_t) &int_33);
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| 215 | idt_setoffset(d++, (uintptr_t) &int_34);
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| 216 | idt_setoffset(d++, (uintptr_t) &int_35);
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| 217 | idt_setoffset(d++, (uintptr_t) &int_36);
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| 218 | idt_setoffset(d++, (uintptr_t) &int_37);
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| 219 | idt_setoffset(d++, (uintptr_t) &int_38);
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| 220 | idt_setoffset(d++, (uintptr_t) &int_39);
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| 221 | idt_setoffset(d++, (uintptr_t) &int_40);
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| 222 | idt_setoffset(d++, (uintptr_t) &int_41);
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| 223 | idt_setoffset(d++, (uintptr_t) &int_42);
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| 224 | idt_setoffset(d++, (uintptr_t) &int_43);
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| 225 | idt_setoffset(d++, (uintptr_t) &int_44);
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| 226 | idt_setoffset(d++, (uintptr_t) &int_45);
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| 227 | idt_setoffset(d++, (uintptr_t) &int_46);
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| 228 | idt_setoffset(d++, (uintptr_t) &int_47);
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| 229 | idt_setoffset(d++, (uintptr_t) &int_48);
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| 230 | idt_setoffset(d++, (uintptr_t) &int_49);
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| 231 | idt_setoffset(d++, (uintptr_t) &int_50);
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| 232 | idt_setoffset(d++, (uintptr_t) &int_51);
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| 233 | idt_setoffset(d++, (uintptr_t) &int_52);
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| 234 | idt_setoffset(d++, (uintptr_t) &int_53);
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| 235 | idt_setoffset(d++, (uintptr_t) &int_54);
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| 236 | idt_setoffset(d++, (uintptr_t) &int_55);
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| 237 | idt_setoffset(d++, (uintptr_t) &int_56);
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| 238 | idt_setoffset(d++, (uintptr_t) &int_57);
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| 239 | idt_setoffset(d++, (uintptr_t) &int_58);
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| 240 | idt_setoffset(d++, (uintptr_t) &int_59);
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| 241 | idt_setoffset(d++, (uintptr_t) &int_60);
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| 242 | idt_setoffset(d++, (uintptr_t) &int_61);
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| 243 | idt_setoffset(d++, (uintptr_t) &int_62);
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| 244 | idt_setoffset(d++, (uintptr_t) &int_63);
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| 245 | }
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| 246 |
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| 247 | /** Initialize segmentation - code/data/idt tables
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| 248 | *
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| 249 | */
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| 250 | void pm_init(void)
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| 251 | {
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| 252 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
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| 253 | tss_descriptor_t *tss_desc;
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| 254 |
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| 255 | /*
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| 256 | * Each CPU has its private GDT and TSS.
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| 257 | * All CPUs share one IDT.
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| 258 | */
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| 259 |
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| 260 | if (config.cpu_active == 1) {
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| 261 | idt_init();
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| 262 | /*
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| 263 | * NOTE: bootstrap CPU has statically allocated TSS, because
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| 264 | * the heap hasn't been initialized so far.
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| 265 | */
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| 266 | tss_p = &tss;
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| 267 | } else {
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| 268 | /* We are going to use malloc, which may return
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| 269 | * non boot-mapped pointer, initialize the CR3 register
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| 270 | * ahead of page_init */
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| 271 | write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
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| 272 |
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| 273 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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| 274 | if (!tss_p)
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| 275 | panic("Cannot allocate TSS.");
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| 276 | }
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| 277 |
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| 278 | tss_initialize(tss_p);
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| 279 |
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| 280 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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| 281 | tss_desc->present = 1;
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| 282 | tss_desc->type = AR_TSS;
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| 283 | tss_desc->dpl = PL_KERNEL;
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| 284 |
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| 285 | gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
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| 286 | gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
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| 287 |
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| 288 | gdtr_load(&gdtr);
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| 289 | idtr_load(&idtr);
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| 290 | /*
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| 291 | * As of this moment, the current CPU has its own GDT pointing
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| 292 | * to its own TSS. We just need to load the TR register.
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| 293 | */
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| 294 | tr_load(GDT_SELECTOR(TSS_DES));
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| 295 | }
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| 296 |
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| 297 | /** @}
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| 298 | */
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