source: mainline/kernel/arch/amd64/src/pm.c@ d8bb821

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d8bb821 was d242cb6, checked in by Martin Decky <martin@…>, 12 years ago

make sure we configure two distinct segment descriptors and set the read bit on the code segment before switching back to real-mode for VESA/VBE
this fixes execution on the latest (3.9.1) Linux KVM with real-mode x86 code emulation that is particularly picky about the code segment permission bits

  • Property mode set to 100644
File size: 8.9 KB
RevLine 
[c245372b]1/*
[4bb31f7]2 * Copyright (c) 2008 Jakub Jermar
[df4ed85]3 * Copyright (c) 2005-2006 Ondrej Palkovsky
[c245372b]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
[dc0b964]30/** @addtogroup amd64
[b45c443]31 * @{
32 */
33/** @file
34 */
35
[f74bbaf]36#include <arch.h>
[c245372b]37#include <arch/pm.h>
[b9e97fb]38#include <arch/asm.h>
[a98cdc7]39#include <mm/as.h>
[b3f8fb7]40#include <mm/frame.h>
[b9e97fb]41#include <memstr.h>
[085d973]42#include <mm/slab.h>
[c245372b]43
44/*
45 * There is no segmentation in long mode so we set up flat mode. In this
46 * mode, we use, for each privilege level, two segments spanning the
47 * whole memory. One is for code and one is for data.
48 */
49
[39cea6a]50descriptor_t gdt[GDT_ITEMS] = {
[c245372b]51 /* NULL descriptor */
52 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
53 /* KTEXT descriptor */
[dc0b964]54 { .limit_0_15 = 0xffffU,
55 .base_0_15 = 0,
56 .base_16_23 = 0,
57 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
58 .limit_16_19 = 0x0fU,
59 .available = 0,
60 .longmode = 1,
[6f878b7]61 .special = 0,
[dc0b964]62 .granularity = 1,
[c245372b]63 .base_24_31 = 0 },
64 /* KDATA descriptor */
[dc0b964]65 { .limit_0_15 = 0xffffU,
66 .base_0_15 = 0,
67 .base_16_23 = 0,
68 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
69 .limit_16_19 = 0x0fU,
70 .available = 0,
71 .longmode = 0,
72 .special = 0,
73 .granularity = 1,
[c245372b]74 .base_24_31 = 0 },
[dd4d6b0]75 /* UDATA descriptor */
[dc0b964]76 { .limit_0_15 = 0xffffU,
77 .base_0_15 = 0,
78 .base_16_23 = 0,
79 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
80 .limit_16_19 = 0x0fU,
81 .available = 0,
82 .longmode = 0,
83 .special = 1,
84 .granularity = 1,
[c245372b]85 .base_24_31 = 0 },
[dd4d6b0]86 /* UTEXT descriptor */
[dc0b964]87 { .limit_0_15 = 0xffffU,
88 .base_0_15 = 0,
89 .base_16_23 = 0,
90 .access = AR_PRESENT | AR_CODE | DPL_USER,
91 .limit_16_19 = 0x0fU,
92 .available = 0,
93 .longmode = 1,
94 .special = 0,
95 .granularity = 1,
[c245372b]96 .base_24_31 = 0 },
[3156582]97 /* KTEXT 32-bit protected, for protected mode before long mode */
[dc0b964]98 { .limit_0_15 = 0xffffU,
99 .base_0_15 = 0,
100 .base_16_23 = 0,
101 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
102 .limit_16_19 = 0x0fU,
103 .available = 0,
104 .longmode = 0,
[946b630]105 .special = 1,
[dc0b964]106 .granularity = 1,
[6f878b7]107 .base_24_31 = 0 },
[b9e97fb]108 /* TSS descriptor - set up will be completed later,
109 * on AMD64 it is 64-bit - 2 items in table */
110 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[de07bcf]111 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
112 /* VESA Init descriptor */
[dc0b964]113#ifdef CONFIG_FB
[d242cb6]114 { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 },
115 { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
[e8194664]116#endif
[c245372b]117};
118
[39cea6a]119idescriptor_t idt[IDT_ITEMS];
[c245372b]120
[4bb31f7]121ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt };
122ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt };
[de25b6f]123
[39cea6a]124static tss_t tss;
125tss_t *tss_p = NULL;
[c245372b]126
[7f1c620]127void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
[b9e97fb]128{
[39cea6a]129 tss_descriptor_t *td = (tss_descriptor_t *) d;
[dc0b964]130
131 td->base_0_15 = base & 0xffffU;
132 td->base_16_23 = ((base) >> 16) & 0xffU;
133 td->base_24_31 = ((base) >> 24) & 0xffU;
[b9e97fb]134 td->base_32_63 = ((base) >> 32);
135}
136
[7f1c620]137void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
[b9e97fb]138{
[99d6fd0]139 tss_descriptor_t *td = (tss_descriptor_t *) d;
140
[dc0b964]141 td->limit_0_15 = limit & 0xffffU;
142 td->limit_16_19 = (limit >> 16) & 0x0fU;
[b9e97fb]143}
144
[7f1c620]145void idt_setoffset(idescriptor_t *d, uintptr_t offset)
[b9e97fb]146{
147 /*
148 * Offset is a linear address.
149 */
[dc0b964]150 d->offset_0_15 = offset & 0xffffU;
151 d->offset_16_31 = (offset >> 16) & 0xffffU;
[b9e97fb]152 d->offset_32_63 = offset >> 32;
153}
154
[39cea6a]155void tss_initialize(tss_t *t)
[b9e97fb]156{
[e32e092]157 memsetb(t, sizeof(tss_t), 0);
[b9e97fb]158}
159
160/*
161 * This function takes care of proper setup of IDT and IDTR.
162 */
163void idt_init(void)
164{
[39cea6a]165 idescriptor_t *d;
[dc0b964]166 unsigned int i;
167
[b9e97fb]168 for (i = 0; i < IDT_ITEMS; i++) {
169 d = &idt[i];
[dc0b964]170
[b9e97fb]171 d->unused = 0;
[1d3d2cf]172 d->selector = GDT_SELECTOR(KTEXT_DES);
[dc0b964]173
[b9e97fb]174 d->present = 1;
[dc0b964]175 d->type = AR_INTERRUPT; /* masking interrupt */
[b9e97fb]176 }
[dc0b964]177
[f77e591d]178 d = &idt[0];
179 idt_setoffset(d++, (uintptr_t) &int_0);
180 idt_setoffset(d++, (uintptr_t) &int_1);
181 idt_setoffset(d++, (uintptr_t) &int_2);
182 idt_setoffset(d++, (uintptr_t) &int_3);
183 idt_setoffset(d++, (uintptr_t) &int_4);
184 idt_setoffset(d++, (uintptr_t) &int_5);
185 idt_setoffset(d++, (uintptr_t) &int_6);
186 idt_setoffset(d++, (uintptr_t) &int_7);
187 idt_setoffset(d++, (uintptr_t) &int_8);
188 idt_setoffset(d++, (uintptr_t) &int_9);
189 idt_setoffset(d++, (uintptr_t) &int_10);
190 idt_setoffset(d++, (uintptr_t) &int_11);
191 idt_setoffset(d++, (uintptr_t) &int_12);
192 idt_setoffset(d++, (uintptr_t) &int_13);
193 idt_setoffset(d++, (uintptr_t) &int_14);
194 idt_setoffset(d++, (uintptr_t) &int_15);
195 idt_setoffset(d++, (uintptr_t) &int_16);
196 idt_setoffset(d++, (uintptr_t) &int_17);
197 idt_setoffset(d++, (uintptr_t) &int_18);
198 idt_setoffset(d++, (uintptr_t) &int_19);
199 idt_setoffset(d++, (uintptr_t) &int_20);
200 idt_setoffset(d++, (uintptr_t) &int_21);
201 idt_setoffset(d++, (uintptr_t) &int_22);
202 idt_setoffset(d++, (uintptr_t) &int_23);
203 idt_setoffset(d++, (uintptr_t) &int_24);
204 idt_setoffset(d++, (uintptr_t) &int_25);
205 idt_setoffset(d++, (uintptr_t) &int_26);
206 idt_setoffset(d++, (uintptr_t) &int_27);
207 idt_setoffset(d++, (uintptr_t) &int_28);
208 idt_setoffset(d++, (uintptr_t) &int_29);
209 idt_setoffset(d++, (uintptr_t) &int_30);
210 idt_setoffset(d++, (uintptr_t) &int_31);
211 idt_setoffset(d++, (uintptr_t) &int_32);
212 idt_setoffset(d++, (uintptr_t) &int_33);
213 idt_setoffset(d++, (uintptr_t) &int_34);
214 idt_setoffset(d++, (uintptr_t) &int_35);
215 idt_setoffset(d++, (uintptr_t) &int_36);
216 idt_setoffset(d++, (uintptr_t) &int_37);
217 idt_setoffset(d++, (uintptr_t) &int_38);
218 idt_setoffset(d++, (uintptr_t) &int_39);
219 idt_setoffset(d++, (uintptr_t) &int_40);
220 idt_setoffset(d++, (uintptr_t) &int_41);
221 idt_setoffset(d++, (uintptr_t) &int_42);
222 idt_setoffset(d++, (uintptr_t) &int_43);
223 idt_setoffset(d++, (uintptr_t) &int_44);
224 idt_setoffset(d++, (uintptr_t) &int_45);
225 idt_setoffset(d++, (uintptr_t) &int_46);
226 idt_setoffset(d++, (uintptr_t) &int_47);
227 idt_setoffset(d++, (uintptr_t) &int_48);
228 idt_setoffset(d++, (uintptr_t) &int_49);
229 idt_setoffset(d++, (uintptr_t) &int_50);
230 idt_setoffset(d++, (uintptr_t) &int_51);
231 idt_setoffset(d++, (uintptr_t) &int_52);
232 idt_setoffset(d++, (uintptr_t) &int_53);
233 idt_setoffset(d++, (uintptr_t) &int_54);
234 idt_setoffset(d++, (uintptr_t) &int_55);
235 idt_setoffset(d++, (uintptr_t) &int_56);
236 idt_setoffset(d++, (uintptr_t) &int_57);
237 idt_setoffset(d++, (uintptr_t) &int_58);
238 idt_setoffset(d++, (uintptr_t) &int_59);
239 idt_setoffset(d++, (uintptr_t) &int_60);
240 idt_setoffset(d++, (uintptr_t) &int_61);
241 idt_setoffset(d++, (uintptr_t) &int_62);
242 idt_setoffset(d++, (uintptr_t) &int_63);
[b9e97fb]243}
244
[49a39c2]245/** Initialize segmentation - code/data/idt tables
246 *
247 */
[b9e97fb]248void pm_init(void)
249{
[99d6fd0]250 descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
[39cea6a]251 tss_descriptor_t *tss_desc;
[99d6fd0]252
[b9e97fb]253 /*
254 * Each CPU has its private GDT and TSS.
255 * All CPUs share one IDT.
256 */
[99d6fd0]257
[b9e97fb]258 if (config.cpu_active == 1) {
259 idt_init();
260 /*
261 * NOTE: bootstrap CPU has statically allocated TSS, because
262 * the heap hasn't been initialized so far.
263 */
264 tss_p = &tss;
[99d6fd0]265 } else {
[a98cdc7]266 /* We are going to use malloc, which may return
267 * non boot-mapped pointer, initialize the CR3 register
268 * ahead of page_init */
[80bcaed]269 write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
[99d6fd0]270
271 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
[b9e97fb]272 if (!tss_p)
[f651e80]273 panic("Cannot allocate TSS.");
[b9e97fb]274 }
[99d6fd0]275
[b9e97fb]276 tss_initialize(tss_p);
[99d6fd0]277
[39cea6a]278 tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
[e291e5d]279 tss_desc->present = 1;
280 tss_desc->type = AR_TSS;
281 tss_desc->dpl = PL_KERNEL;
[b9e97fb]282
[7f1c620]283 gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
[11928d5]284 gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
[99d6fd0]285
[897ad60]286 gdtr_load(&gdtr);
287 idtr_load(&idtr);
[b9e97fb]288 /*
289 * As of this moment, the current CPU has its own GDT pointing
290 * to its own TSS. We just need to load the TR register.
291 */
[1d3d2cf]292 tr_load(GDT_SELECTOR(TSS_DES));
[b9e97fb]293}
[b45c443]294
[06e1e95]295/** @}
[b45c443]296 */
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