source: mainline/kernel/arch/amd64/src/interrupt.c@ 0d1e976

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0d1e976 was 9171f12, checked in by Jakub Jermar <jakub@…>, 15 years ago

Make istate_decode() print all amd64 GPRs.

  • Property mode set to 100644
File size: 6.1 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/interrupt.h>
36#include <print.h>
37#include <debug.h>
38#include <panic.h>
39#include <arch/drivers/i8259.h>
40#include <func.h>
41#include <cpu.h>
42#include <arch/asm.h>
43#include <mm/tlb.h>
44#include <mm/as.h>
45#include <arch.h>
46#include <arch/asm.h>
47#include <proc/scheduler.h>
48#include <proc/thread.h>
49#include <proc/task.h>
50#include <synch/spinlock.h>
51#include <arch/ddi/ddi.h>
52#include <interrupt.h>
53#include <ddi/irq.h>
54#include <symtab.h>
55#include <stacktrace.h>
56
57/*
58 * Interrupt and exception dispatching.
59 */
60
61void (* disable_irqs_function)(uint16_t irqmask) = NULL;
62void (* enable_irqs_function)(uint16_t irqmask) = NULL;
63void (* eoi_function)(void) = NULL;
64
65void istate_decode(istate_t *istate)
66{
67 printf("cs =%p\trip=%p\trfl=%p\terr=%p\n",
68 istate->cs, istate->rip, istate->rflags, istate->error_word);
69
70 if (istate_from_uspace(istate))
71 printf("ss =%p\n", istate->ss);
72
73 printf("rax=%p\trbx=%p\trcx=%p\trdx=%p\n",
74 istate->rax, istate->rbx, istate->rcx, istate->rdx);
75 printf("rsi=%p\trdi=%p\trbp=%p\trsp=%p\n",
76 istate->rsi, istate->rdi, istate->rbp,
77 istate_from_uspace(istate) ? istate->rsp : (uintptr_t)&istate->rsp);
78 printf("r8 =%p\tr9 =%p\tr10=%p\tr11=%p\n",
79 istate->r8, istate->r9, istate->r10, istate->r11);
80 printf("r12=%p\tr13=%p\tr14=%p\tr15=%p\n",
81 istate->r12, istate->r13, istate->r14, istate->r15);
82}
83
84static void trap_virtual_eoi(void)
85{
86 if (eoi_function)
87 eoi_function();
88 else
89 panic("No eoi_function.");
90
91}
92
93static void null_interrupt(unsigned int n, istate_t *istate)
94{
95 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
96 panic_badtrap(istate, n, "Unserviced interrupt.");
97}
98
99static void de_fault(unsigned int n, istate_t *istate)
100{
101 fault_if_from_uspace(istate, "Divide error.");
102 panic_badtrap(istate, n, "Divide error.");
103}
104
105/** General Protection Fault.
106 *
107 */
108static void gp_fault(unsigned int n, istate_t *istate)
109{
110 if (TASK) {
111 irq_spinlock_lock(&TASK->lock, false);
112 size_t ver = TASK->arch.iomapver;
113 irq_spinlock_unlock(&TASK->lock, false);
114
115 if (CPU->arch.iomapver_copy != ver) {
116 /*
117 * This fault can be caused by an early access
118 * to I/O port because of an out-dated
119 * I/O Permission bitmap installed on CPU.
120 * Install the fresh copy and restart
121 * the instruction.
122 */
123 io_perm_bitmap_install();
124 return;
125 }
126 fault_if_from_uspace(istate, "General protection fault.");
127 }
128 panic_badtrap(istate, n, "General protection fault.");
129}
130
131static void ss_fault(unsigned int n, istate_t *istate)
132{
133 fault_if_from_uspace(istate, "Stack fault.");
134 panic_badtrap(istate, n, "Stack fault.");
135}
136
137static void nm_fault(unsigned int n, istate_t *istate)
138{
139#ifdef CONFIG_FPU_LAZY
140 scheduler_fpu_lazy_request();
141#else
142 fault_if_from_uspace(istate, "FPU fault.");
143 panic("FPU fault.");
144#endif
145}
146
147#ifdef CONFIG_SMP
148static void tlb_shootdown_ipi(unsigned int n, istate_t *istate)
149{
150 trap_virtual_eoi();
151 tlb_shootdown_ipi_recv();
152}
153#endif
154
155/** Handler of IRQ exceptions.
156 *
157 */
158static void irq_interrupt(unsigned int n, istate_t *istate)
159{
160 ASSERT(n >= IVT_IRQBASE);
161
162 unsigned int inum = n - IVT_IRQBASE;
163 bool ack = false;
164 ASSERT(inum < IRQ_COUNT);
165 ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
166
167 irq_t *irq = irq_dispatch_and_lock(inum);
168 if (irq) {
169 /*
170 * The IRQ handler was found.
171 */
172
173 if (irq->preack) {
174 /* Send EOI before processing the interrupt */
175 trap_virtual_eoi();
176 ack = true;
177 }
178 irq->handler(irq);
179 irq_spinlock_unlock(&irq->lock, false);
180 } else {
181 /*
182 * Spurious interrupt.
183 */
184#ifdef CONFIG_DEBUG
185 printf("cpu%u: spurious interrupt (inum=%u)\n", CPU->id, inum);
186#endif
187 }
188
189 if (!ack)
190 trap_virtual_eoi();
191}
192
193void interrupt_init(void)
194{
195 unsigned int i;
196
197 for (i = 0; i < IVT_ITEMS; i++)
198 exc_register(i, "null", false, (iroutine_t) null_interrupt);
199
200 for (i = 0; i < IRQ_COUNT; i++) {
201 if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
202 exc_register(IVT_IRQBASE + i, "irq", true,
203 (iroutine_t) irq_interrupt);
204 }
205
206 exc_register(0, "de_fault", true, (iroutine_t) de_fault);
207 exc_register(7, "nm_fault", true, (iroutine_t) nm_fault);
208 exc_register(12, "ss_fault", true, (iroutine_t) ss_fault);
209 exc_register(13, "gp_fault", true, (iroutine_t) gp_fault);
210
211#ifdef CONFIG_SMP
212 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
213 (iroutine_t) tlb_shootdown_ipi);
214#endif
215}
216
217void trap_virtual_enable_irqs(uint16_t irqmask)
218{
219 if (enable_irqs_function)
220 enable_irqs_function(irqmask);
221 else
222 panic("No enable_irqs_function.");
223}
224
225void trap_virtual_disable_irqs(uint16_t irqmask)
226{
227 if (disable_irqs_function)
228 disable_irqs_function(irqmask);
229 else
230 panic("No disable_irqs_function.");
231}
232
233/** @}
234 */
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