[db3341e] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[db3341e] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_amd64_interrupt
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[db3341e] | 35 | #include <arch/interrupt.h>
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[63e27ef] | 36 | #include <assert.h>
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[b2fa1204] | 37 | #include <log.h>
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[db3341e] | 38 | #include <panic.h>
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[80d31883] | 39 | #include <arch/drivers/i8259.h>
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[b2e121a] | 40 | #include <halt.h>
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[db3341e] | 41 | #include <cpu.h>
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| 42 | #include <arch/asm.h>
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| 43 | #include <mm/tlb.h>
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[20d50a1] | 44 | #include <mm/as.h>
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[db3341e] | 45 | #include <arch.h>
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[b49f4ae] | 46 | #include <proc/scheduler.h>
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[1084a784] | 47 | #include <proc/thread.h>
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[2382d09] | 48 | #include <proc/task.h>
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| 49 | #include <synch/spinlock.h>
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| 50 | #include <arch/ddi/ddi.h>
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[5626277] | 51 | #include <interrupt.h>
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[8607db8] | 52 | #include <ddi/irq.h>
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[e2b762ec] | 53 | #include <symtab.h>
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[304342e] | 54 | #include <stacktrace.h>
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[2ee1ccc] | 55 | #include <smp/smp_call.h>
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[e2b762ec] | 56 |
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[8607db8] | 57 | /*
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| 58 | * Interrupt and exception dispatching.
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| 59 | */
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| 60 |
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[1433ecda] | 61 | void (*disable_irqs_function)(uint16_t irqmask) = NULL;
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| 62 | void (*enable_irqs_function)(uint16_t irqmask) = NULL;
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| 63 | void (*eoi_function)(void) = NULL;
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[acc7ce4] | 64 | const char *irqs_info = NULL;
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[8607db8] | 65 |
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[22a28a69] | 66 | void istate_decode(istate_t *istate)
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[8ec9bae] | 67 | {
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[b2fa1204] | 68 | log_printf("cs =%0#18" PRIx64 "\trip=%0#18" PRIx64 "\t"
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[2438fa6] | 69 | "rfl=%0#18" PRIx64 "\terr=%0#18" PRIx64 "\n",
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| 70 | istate->cs, istate->rip, istate->rflags, istate->error_word);
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[a35b458] | 71 |
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[9171f12] | 72 | if (istate_from_uspace(istate))
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[b2fa1204] | 73 | log_printf("ss =%0#18" PRIx64 "\n", istate->ss);
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[a35b458] | 74 |
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[b2fa1204] | 75 | log_printf("rax=%0#18" PRIx64 "\trbx=%0#18" PRIx64 "\t"
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[2438fa6] | 76 | "rcx=%0#18" PRIx64 "\trdx=%0#18" PRIx64 "\n",
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[9171f12] | 77 | istate->rax, istate->rbx, istate->rcx, istate->rdx);
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[a35b458] | 78 |
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[b2fa1204] | 79 | log_printf("rsi=%0#18" PRIx64 "\trdi=%0#18" PRIx64 "\t"
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[2438fa6] | 80 | "rbp=%0#18" PRIx64 "\trsp=%0#18" PRIx64 "\n",
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| 81 | istate->rsi, istate->rdi, istate->rbp,
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| 82 | istate_from_uspace(istate) ? istate->rsp :
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| 83 | (uintptr_t) &istate->rsp);
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[a35b458] | 84 |
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[b2fa1204] | 85 | log_printf("r8 =%0#18" PRIx64 "\tr9 =%0#18" PRIx64 "\t"
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[2438fa6] | 86 | "r10=%0#18" PRIx64 "\tr11=%0#18" PRIx64 "\n",
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[9171f12] | 87 | istate->r8, istate->r9, istate->r10, istate->r11);
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[a35b458] | 88 |
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[b2fa1204] | 89 | log_printf("r12=%0#18" PRIx64 "\tr13=%0#18" PRIx64 "\t"
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[2438fa6] | 90 | "r14=%0#18" PRIx64 "\tr15=%0#18" PRIx64 "\n",
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[9171f12] | 91 | istate->r12, istate->r13, istate->r14, istate->r15);
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[8ec9bae] | 92 | }
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[db3341e] | 93 |
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[8607db8] | 94 | static void trap_virtual_eoi(void)
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| 95 | {
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| 96 | if (eoi_function)
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| 97 | eoi_function();
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| 98 | else
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[f651e80] | 99 | panic("No eoi_function.");
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[db3341e] | 100 |
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[8607db8] | 101 | }
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[db3341e] | 102 |
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[214ec25c] | 103 | static void null_interrupt(unsigned int n, istate_t *istate)
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[db3341e] | 104 | {
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[214ec25c] | 105 | fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
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[a043e39] | 106 | panic_badtrap(istate, n, "Unserviced interrupt.");
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[db3341e] | 107 | }
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| 108 |
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[214ec25c] | 109 | static void de_fault(unsigned int n, istate_t *istate)
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[4491338] | 110 | {
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| 111 | fault_if_from_uspace(istate, "Divide error.");
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[a043e39] | 112 | panic_badtrap(istate, n, "Divide error.");
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[4491338] | 113 | }
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| 114 |
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[da1bafb] | 115 | /** General Protection Fault.
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| 116 | *
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| 117 | */
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[214ec25c] | 118 | static void gp_fault(unsigned int n, istate_t *istate)
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[db3341e] | 119 | {
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[2382d09] | 120 | if (TASK) {
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[da1bafb] | 121 | irq_spinlock_lock(&TASK->lock, false);
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| 122 | size_t ver = TASK->arch.iomapver;
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| 123 | irq_spinlock_unlock(&TASK->lock, false);
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[a35b458] | 124 |
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[2382d09] | 125 | if (CPU->arch.iomapver_copy != ver) {
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| 126 | /*
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| 127 | * This fault can be caused by an early access
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| 128 | * to I/O port because of an out-dated
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| 129 | * I/O Permission bitmap installed on CPU.
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| 130 | * Install the fresh copy and restart
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| 131 | * the instruction.
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| 132 | */
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| 133 | io_perm_bitmap_install();
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| 134 | return;
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| 135 | }
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[f651e80] | 136 | fault_if_from_uspace(istate, "General protection fault.");
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[2382d09] | 137 | }
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[a043e39] | 138 | panic_badtrap(istate, n, "General protection fault.");
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[db3341e] | 139 | }
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| 140 |
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[214ec25c] | 141 | static void ss_fault(unsigned int n, istate_t *istate)
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[db3341e] | 142 | {
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[f651e80] | 143 | fault_if_from_uspace(istate, "Stack fault.");
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[a043e39] | 144 | panic_badtrap(istate, n, "Stack fault.");
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[db3341e] | 145 | }
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| 146 |
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[214ec25c] | 147 | static void nm_fault(unsigned int n, istate_t *istate)
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[db3341e] | 148 | {
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[6da1013f] | 149 | #ifdef CONFIG_FPU_LAZY
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[b49f4ae] | 150 | scheduler_fpu_lazy_request();
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| 151 | #else
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[f651e80] | 152 | fault_if_from_uspace(istate, "FPU fault.");
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| 153 | panic("FPU fault.");
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[b49f4ae] | 154 | #endif
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[db3341e] | 155 | }
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| 156 |
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[cbc8ac6] | 157 | #ifdef CONFIG_SMP
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[214ec25c] | 158 | static void tlb_shootdown_ipi(unsigned int n, istate_t *istate)
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[db3341e] | 159 | {
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| 160 | trap_virtual_eoi();
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| 161 | tlb_shootdown_ipi_recv();
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| 162 | }
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[2ee1ccc] | 163 |
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| 164 | static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
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| 165 | {
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| 166 | trap_virtual_eoi();
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| 167 | smp_call_ipi_recv();
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| 168 | }
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[cbc8ac6] | 169 | #endif
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[db3341e] | 170 |
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[da1bafb] | 171 | /** Handler of IRQ exceptions.
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| 172 | *
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| 173 | */
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[214ec25c] | 174 | static void irq_interrupt(unsigned int n, istate_t *istate)
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[8607db8] | 175 | {
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[63e27ef] | 176 | assert(n >= IVT_IRQBASE);
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[a35b458] | 177 |
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[214ec25c] | 178 | unsigned int inum = n - IVT_IRQBASE;
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[7bcfbbc] | 179 | bool ack = false;
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[63e27ef] | 180 | assert(inum < IRQ_COUNT);
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| 181 | assert((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
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[a35b458] | 182 |
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[8607db8] | 183 | irq_t *irq = irq_dispatch_and_lock(inum);
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| 184 | if (irq) {
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| 185 | /*
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| 186 | * The IRQ handler was found.
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| 187 | */
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[a35b458] | 188 |
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[7bcfbbc] | 189 | if (irq->preack) {
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| 190 | /* Send EOI before processing the interrupt */
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| 191 | trap_virtual_eoi();
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| 192 | ack = true;
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| 193 | }
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[6cd9aa6] | 194 | irq->handler(irq);
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[da1bafb] | 195 | irq_spinlock_unlock(&irq->lock, false);
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[8607db8] | 196 | } else {
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| 197 | /*
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| 198 | * Spurious interrupt.
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| 199 | */
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| 200 | #ifdef CONFIG_DEBUG
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[b2fa1204] | 201 | log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt (inum=%u)",
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| 202 | CPU->id, inum);
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[8607db8] | 203 | #endif
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| 204 | }
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[a35b458] | 205 |
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[7bcfbbc] | 206 | if (!ack)
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| 207 | trap_virtual_eoi();
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[8607db8] | 208 | }
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| 209 |
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| 210 | void interrupt_init(void)
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| 211 | {
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[b3b7e14a] | 212 | unsigned int i;
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[a35b458] | 213 |
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[8607db8] | 214 | for (i = 0; i < IVT_ITEMS; i++)
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[b3b7e14a] | 215 | exc_register(i, "null", false, (iroutine_t) null_interrupt);
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[a35b458] | 216 |
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[8607db8] | 217 | for (i = 0; i < IRQ_COUNT; i++) {
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| 218 | if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
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[b3b7e14a] | 219 | exc_register(IVT_IRQBASE + i, "irq", true,
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| 220 | (iroutine_t) irq_interrupt);
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[8607db8] | 221 | }
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[a35b458] | 222 |
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[4b0206c] | 223 | exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
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| 224 | exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
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| 225 | exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
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| 226 | exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
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[a35b458] | 227 |
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[8607db8] | 228 | #ifdef CONFIG_SMP
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[b3b7e14a] | 229 | exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
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| 230 | (iroutine_t) tlb_shootdown_ipi);
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[1b20da0] | 231 | exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
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[1433ecda] | 232 | (iroutine_t) arch_smp_call_ipi_recv);
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[8607db8] | 233 | #endif
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| 234 | }
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| 235 |
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[7f1c620] | 236 | void trap_virtual_enable_irqs(uint16_t irqmask)
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[db3341e] | 237 | {
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| 238 | if (enable_irqs_function)
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| 239 | enable_irqs_function(irqmask);
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| 240 | else
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[f651e80] | 241 | panic("No enable_irqs_function.");
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[db3341e] | 242 | }
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| 243 |
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[7f1c620] | 244 | void trap_virtual_disable_irqs(uint16_t irqmask)
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[db3341e] | 245 | {
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| 246 | if (disable_irqs_function)
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| 247 | disable_irqs_function(irqmask);
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| 248 | else
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[f651e80] | 249 | panic("No disable_irqs_function.");
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[db3341e] | 250 | }
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| 251 |
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[06e1e95] | 252 | /** @}
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[b45c443] | 253 | */
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