| 1 | /*
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| 2 | * Copyright (c) 2005 Ondrej Palkovsky
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #define IREGISTER_SPACE 80
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| 30 |
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| 31 | #define IOFFSET_RAX 0x00
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| 32 | #define IOFFSET_RCX 0x08
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| 33 | #define IOFFSET_RDX 0x10
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| 34 | #define IOFFSET_RSI 0x18
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| 35 | #define IOFFSET_RDI 0x20
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| 36 | #define IOFFSET_R8 0x28
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| 37 | #define IOFFSET_R9 0x30
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| 38 | #define IOFFSET_R10 0x38
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| 39 | #define IOFFSET_R11 0x40
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| 40 | #define IOFFSET_RBP 0x48
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| 41 |
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| 42 | /**
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| 43 | * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int
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| 44 | * has no error word and 1 means interrupt with error word
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| 45 | *
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| 46 | */
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| 47 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00
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| 48 |
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| 49 | #include <arch/pm.h>
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| 50 | #include <arch/mm/page.h>
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| 51 |
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| 52 | .text
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| 53 | .global interrupt_handlers
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| 54 | .global syscall_entry
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| 55 | .global cpuid
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| 56 | .global has_cpuid
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| 57 | .global read_efer_flag
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| 58 | .global set_efer_flag
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| 59 | .global memsetb
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| 60 | .global memsetw
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| 61 | .global memcpy
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| 62 | .global memcpy_from_uspace
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| 63 | .global memcpy_to_uspace
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| 64 | .global memcpy_from_uspace_failover_address
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| 65 | .global memcpy_to_uspace_failover_address
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| 66 |
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| 67 | /* Wrapper for generic memsetb */
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| 68 | memsetb:
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| 69 | jmp _memsetb
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| 70 |
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| 71 | /* Wrapper for generic memsetw */
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| 72 | memsetw:
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| 73 | jmp _memsetw
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| 74 |
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| 75 | #define MEMCPY_DST %rdi
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| 76 | #define MEMCPY_SRC %rsi
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| 77 | #define MEMCPY_SIZE %rdx
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| 78 |
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| 79 | /**
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| 80 | * Copy memory from/to userspace.
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| 81 | *
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| 82 | * This is almost conventional memcpy().
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| 83 | * The difference is that there is a failover part
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| 84 | * to where control is returned from a page fault if
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| 85 | * the page fault occurs during copy_from_uspace()
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| 86 | * or copy_to_uspace().
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| 87 | *
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| 88 | * @param MEMCPY_DST Destination address.
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| 89 | * @param MEMCPY_SRC Source address.
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| 90 | * @param MEMCPY_SIZE Number of bytes to copy.
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| 91 | *
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| 92 | * @retrun MEMCPY_DST on success, 0 on failure.
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| 93 | *
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| 94 | */
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| 95 | memcpy:
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| 96 | memcpy_from_uspace:
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| 97 | memcpy_to_uspace:
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| 98 | movq MEMCPY_DST, %rax
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| 99 |
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| 100 | movq MEMCPY_SIZE, %rcx
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| 101 | shrq $3, %rcx /* size / 8 */
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| 102 |
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| 103 | rep movsq /* copy as much as possible word by word */
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| 104 |
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| 105 | movq MEMCPY_SIZE, %rcx
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| 106 | andq $7, %rcx /* size % 8 */
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| 107 | jz 0f
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| 108 |
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| 109 | rep movsb /* copy the rest byte by byte */
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| 110 |
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| 111 | 0:
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| 112 | ret /* return MEMCPY_SRC, success */
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| 113 |
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| 114 | memcpy_from_uspace_failover_address:
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| 115 | memcpy_to_uspace_failover_address:
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| 116 | xorq %rax, %rax /* return 0, failure */
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| 117 | ret
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| 118 |
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| 119 | /** Determine CPUID support
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| 120 | *
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| 121 | * @return 0 in EAX if CPUID is not support, 1 if supported.
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| 122 | *
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| 123 | */
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| 124 | has_cpuid:
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| 125 | /* Load RFLAGS */
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| 126 | pushfq
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| 127 | popq %rax
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| 128 | movq %rax, %rdx
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| 129 |
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| 130 | /* Flip the ID bit */
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| 131 | btcl $21, %edx
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| 132 |
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| 133 | /* Store RFLAGS */
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| 134 | pushq %rdx
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| 135 | popfq
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| 136 | pushfq
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| 137 |
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| 138 | /* Get the ID bit again */
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| 139 | popq %rdx
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| 140 | andl $(1 << 21), %eax
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| 141 | andl $(1 << 21), %edx
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| 142 |
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| 143 | /* 0 if not supported, 1 if supported */
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| 144 | xorl %edx, %eax
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| 145 | ret
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| 146 |
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| 147 | cpuid:
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| 148 | /* Preserve %rbx across function calls */
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| 149 | movq %rbx, %r10
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| 150 |
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| 151 | /* Load the command into %eax */
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| 152 | movl %edi, %eax
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| 153 |
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| 154 | cpuid
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| 155 | movl %eax, 0(%rsi)
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| 156 | movl %ebx, 4(%rsi)
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| 157 | movl %ecx, 8(%rsi)
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| 158 | movl %edx, 12(%rsi)
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| 159 |
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| 160 | movq %r10, %rbx
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| 161 | ret
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| 162 |
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| 163 | set_efer_flag:
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| 164 | movq $0xc0000080, %rcx
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| 165 | rdmsr
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| 166 | btsl %edi, %eax
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| 167 | wrmsr
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| 168 | ret
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| 169 |
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| 170 | read_efer_flag:
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| 171 | movq $0xc0000080, %rcx
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| 172 | rdmsr
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| 173 | ret
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| 174 |
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| 175 | /** Push all volatile general purpose registers on stack
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| 176 | *
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| 177 | */
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| 178 | .macro save_all_gpr
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| 179 | movq %rax, IOFFSET_RAX(%rsp)
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| 180 | movq %rcx, IOFFSET_RCX(%rsp)
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| 181 | movq %rdx, IOFFSET_RDX(%rsp)
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| 182 | movq %rsi, IOFFSET_RSI(%rsp)
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| 183 | movq %rdi, IOFFSET_RDI(%rsp)
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| 184 | movq %r8, IOFFSET_R8(%rsp)
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| 185 | movq %r9, IOFFSET_R9(%rsp)
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| 186 | movq %r10, IOFFSET_R10(%rsp)
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| 187 | movq %r11, IOFFSET_R11(%rsp)
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| 188 | movq %rbp, IOFFSET_RBP(%rsp)
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| 189 | .endm
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| 190 |
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| 191 | .macro restore_all_gpr
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| 192 | movq IOFFSET_RAX(%rsp), %rax
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| 193 | movq IOFFSET_RCX(%rsp), %rcx
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| 194 | movq IOFFSET_RDX(%rsp), %rdx
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| 195 | movq IOFFSET_RSI(%rsp), %rsi
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| 196 | movq IOFFSET_RDI(%rsp), %rdi
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| 197 | movq IOFFSET_R8(%rsp), %r8
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| 198 | movq IOFFSET_R9(%rsp), %r9
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| 199 | movq IOFFSET_R10(%rsp), %r10
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| 200 | movq IOFFSET_R11(%rsp), %r11
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| 201 | movq IOFFSET_RBP(%rsp), %rbp
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| 202 | .endm
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| 203 |
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| 204 | #define INTERRUPT_ALIGN 128
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| 205 |
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| 206 | /** Declare interrupt handlers
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| 207 | *
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| 208 | * Declare interrupt handlers for n interrupt
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| 209 | * vectors starting at vector i.
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| 210 | *
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| 211 | * The handlers call exc_dispatch().
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| 212 | *
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| 213 | */
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| 214 | .macro handler i n
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| 215 |
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| 216 | /*
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| 217 | * Choose between version with error code and version without error
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| 218 | * code. Both versions have to be of the same size. amd64 assembly is,
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| 219 | * however, a little bit tricky. For instance, subq $0x80, %rsp and
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| 220 | * subq $0x78, %rsp can result in two instructions with different
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| 221 | * op-code lengths.
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| 222 | * Therefore we align the interrupt handlers.
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| 223 | */
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| 224 |
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| 225 | .iflt \i-32
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| 226 | .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
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| 227 | /*
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| 228 | * Version with error word.
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| 229 | */
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| 230 | subq $IREGISTER_SPACE, %rsp
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| 231 | .else
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| 232 | /*
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| 233 | * Version without error word,
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| 234 | */
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| 235 | subq $(IREGISTER_SPACE + 8), %rsp
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| 236 | .endif
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| 237 | .else
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| 238 | /*
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| 239 | * Version without error word,
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| 240 | */
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| 241 | subq $(IREGISTER_SPACE + 8), %rsp
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| 242 | .endif
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| 243 |
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| 244 | save_all_gpr
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| 245 | cld
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| 246 |
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| 247 | /*
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| 248 | * Stop stack traces here if we came from userspace.
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| 249 | */
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| 250 | movq %cs, %rax
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| 251 | xorq %rdx, %rdx
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| 252 | cmpq %rax, IREGISTER_SPACE+16(%rsp)
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| 253 | cmovneq %rdx, %rbp
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| 254 |
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| 255 | movq $(\i), %rdi /* %rdi - first argument */
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| 256 | movq %rsp, %rsi /* %rsi - pointer to istate */
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| 257 |
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| 258 | /* Call exc_dispatch(i, istate) */
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| 259 | call exc_dispatch
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| 260 |
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| 261 | restore_all_gpr
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| 262 |
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| 263 | /* $8 = Skip error word */
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| 264 | addq $(IREGISTER_SPACE + 8), %rsp
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| 265 | iretq
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| 266 |
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| 267 | .align INTERRUPT_ALIGN
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| 268 | .if (\n - \i) - 1
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| 269 | handler "(\i + 1)", \n
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| 270 | .endif
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| 271 | .endm
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| 272 |
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| 273 | .align INTERRUPT_ALIGN
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| 274 | interrupt_handlers:
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| 275 | h_start:
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| 276 | handler 0 IDT_ITEMS
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| 277 | h_end:
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| 278 |
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| 279 | /** Low-level syscall handler
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| 280 | *
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| 281 | * Registers on entry:
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| 282 | *
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| 283 | * @param %rcx Userspace return address.
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| 284 | * @param %r11 Userspace RLFAGS.
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| 285 | *
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| 286 | * @param %rax Syscall number.
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| 287 | * @param %rdi 1st syscall argument.
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| 288 | * @param %rsi 2nd syscall argument.
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| 289 | * @param %rdx 3rd syscall argument.
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| 290 | * @param %r10 4th syscall argument. Used instead of RCX because
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| 291 | * the SYSCALL instruction clobbers it.
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| 292 | * @param %r8 5th syscall argument.
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| 293 | * @param %r9 6th syscall argument.
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| 294 | *
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| 295 | * @return Return value is in %rax.
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| 296 | *
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| 297 | */
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| 298 | syscall_entry:
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| 299 | /* Switch to hidden %gs */
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| 300 | swapgs
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| 301 |
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| 302 | /*
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| 303 | * %gs:0 Scratch space for this thread's user RSP
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| 304 | * %gs:8 Address to be used as this thread's kernel RSP
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| 305 | */
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| 306 |
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| 307 | movq %rsp, %gs:0 /* save this thread's user RSP */
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| 308 | movq %gs:8, %rsp /* set this thread's kernel RSP */
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| 309 |
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| 310 | /* Switch back to remain consistent */
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| 311 | swapgs
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| 312 | sti
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| 313 |
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| 314 | pushq %rcx
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| 315 | pushq %r11
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| 316 | pushq %rbp
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| 317 |
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| 318 | xorq %rbp, %rbp /* stop the stack traces here */
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| 319 |
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| 320 | /* Copy the 4th argument where it is expected */
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| 321 | movq %r10, %rcx
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| 322 | pushq %rax
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| 323 |
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| 324 | call syscall_handler
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| 325 |
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| 326 | addq $8, %rsp
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| 327 |
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| 328 | popq %rbp
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| 329 | popq %r11
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| 330 | popq %rcx
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| 331 |
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| 332 | cli
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| 333 | swapgs
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| 334 |
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| 335 | /* Restore the user RSP */
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| 336 | movq %gs:0, %rsp
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| 337 | swapgs
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| 338 |
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| 339 | sysretq
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| 340 |
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| 341 | .data
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| 342 | .global interrupt_handler_size
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| 343 |
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| 344 | interrupt_handler_size: .quad (h_end - h_start) / IDT_ITEMS
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