source: mainline/kernel/arch/amd64/include/mm/page.h@ e40ece98

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e40ece98 was c0699467, checked in by Martin Decky <martin@…>, 14 years ago

do not provide general access to kernel headers from uspace, only allow specific headers to be accessed or shared
externalize headers which serve as kernel/uspace API/ABI into a special tree

  • Property mode set to 100644
File size: 7.6 KB
RevLine 
[1141c1a]1/*
[df4ed85]2 * Copyright (c) 2005 Ondrej Palkovsky
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7f1c620]29/** @addtogroup amd64mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[93165be]35/** Paging on AMD64
36 *
[a1f60f3]37 * The space is divided in positive numbers (uspace) and
38 * negative numbers (kernel). The 'negative' space starting
39 * with 0xffff800000000000 and ending with 0xffffffffffffffff
40 * is identically mapped physical memory.
[93165be]41 *
42 */
43
[06e1e95]44#ifndef KERN_amd64_PAGE_H_
45#define KERN_amd64_PAGE_H_
[1141c1a]46
[fa2d382]47#include <arch/mm/frame.h>
[7a0359b]48#include <trace.h>
[fa2d382]49
[a1f60f3]50#define PAGE_WIDTH FRAME_WIDTH
51#define PAGE_SIZE FRAME_SIZE
[d1f8a87]52
[8fc0d455]53#ifndef __ASM__
[1141c1a]54
[dc0b964]55#define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
56#define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
[b3f8fb7]57
[a1f60f3]58#else /* __ASM__ */
59
60#define KA2PA(x) ((x) - 0xffff800000000000)
61#define PA2KA(x) ((x) + 0xffff800000000000)
62
63#endif /* __ASM__ */
[8fc0d455]64
[c03ee1c]65/* Number of entries in each level. */
[a1f60f3]66#define PTL0_ENTRIES_ARCH 512
67#define PTL1_ENTRIES_ARCH 512
68#define PTL2_ENTRIES_ARCH 512
69#define PTL3_ENTRIES_ARCH 512
[ecbdc724]70
[c03ee1c]71/* Page table sizes for each level. */
[a1f60f3]72#define PTL0_SIZE_ARCH ONE_FRAME
73#define PTL1_SIZE_ARCH ONE_FRAME
74#define PTL2_SIZE_ARCH ONE_FRAME
75#define PTL3_SIZE_ARCH ONE_FRAME
[c03ee1c]76
77/* Macros calculating indices into page tables in each level. */
[dc0b964]78#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ffU)
79#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ffU)
80#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ffU)
81#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ffU)
[c03ee1c]82
83/* Get PTE address accessors for each level. */
84#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
85 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
86 (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
87#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
88 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
89 (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
90#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
91 ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
92 (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
93#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
94 ((uintptr_t *) \
95 ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
96 (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
97
98/* Set PTE address accessors for each level. */
99#define SET_PTL0_ADDRESS_ARCH(ptl0) \
100 (write_cr3((uintptr_t) (ptl0)))
101#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
[98000fb]102 set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
[c03ee1c]103#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
[98000fb]104 set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
[c03ee1c]105#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
[98000fb]106 set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
[c03ee1c]107#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
[98000fb]108 set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
[c03ee1c]109
110/* Get PTE flags accessors for each level. */
111#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
[98000fb]112 get_pt_flags((pte_t *) (ptl0), (size_t) (i))
[c03ee1c]113#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
[98000fb]114 get_pt_flags((pte_t *) (ptl1), (size_t) (i))
[c03ee1c]115#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
[98000fb]116 get_pt_flags((pte_t *) (ptl2), (size_t) (i))
[c03ee1c]117#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
[98000fb]118 get_pt_flags((pte_t *) (ptl3), (size_t) (i))
[c03ee1c]119
120/* Set PTE flags accessors for each level. */
121#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
[98000fb]122 set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
[c03ee1c]123#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
[98000fb]124 set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
[c03ee1c]125#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
[98000fb]126 set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
[c03ee1c]127#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
[98000fb]128 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
[c03ee1c]129
130/* Macros for querying the last-level PTE entries. */
131#define PTE_VALID_ARCH(p) \
132 (*((uint64_t *) (p)) != 0)
133#define PTE_PRESENT_ARCH(p) \
134 ((p)->present != 0)
135#define PTE_GET_FRAME_ARCH(p) \
136 ((((uintptr_t) (p)->addr_12_31) << 12) | \
137 ((uintptr_t) (p)->addr_32_51 << 32))
138#define PTE_WRITABLE_ARCH(p) \
139 ((p)->writeable != 0)
140#define PTE_EXECUTABLE_ARCH(p) \
141 ((p)->no_execute == 0)
[ecbdc724]142
[8fc0d455]143#ifndef __ASM__
[db3341e]144
[a1f60f3]145#include <mm/mm.h>
146#include <arch/interrupt.h>
147#include <typedefs.h>
148
[567807b1]149/* Page fault error codes. */
150
[c03ee1c]151/** When bit on this position is 0, the page fault was caused by a not-present
152 * page.
153 */
[a1f60f3]154#define PFERR_CODE_P (1 << 0)
[567807b1]155
156/** When bit on this position is 1, the page fault was caused by a write. */
[a1f60f3]157#define PFERR_CODE_RW (1 << 1)
[567807b1]158
159/** When bit on this position is 1, the page fault was caused in user mode. */
[a1f60f3]160#define PFERR_CODE_US (1 << 2)
[567807b1]161
162/** When bit on this position is 1, a reserved bit was set in page directory. */
[a1f60f3]163#define PFERR_CODE_RSVD (1 << 3)
[567807b1]164
[c03ee1c]165/** When bit on this position os 1, the page fault was caused during instruction
166 * fecth.
167 */
[a1f60f3]168#define PFERR_CODE_ID (1 << 4)
[567807b1]169
[33be9ac]170/** Page Table Entry. */
171typedef struct {
[a1f60f3]172 unsigned int present : 1;
173 unsigned int writeable : 1;
174 unsigned int uaccessible : 1;
175 unsigned int page_write_through : 1;
176 unsigned int page_cache_disable : 1;
177 unsigned int accessed : 1;
178 unsigned int dirty : 1;
179 unsigned int unused: 1;
180 unsigned int global : 1;
181 unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */
182 unsigned int avl : 2;
183 unsigned int addr_12_31 : 30;
184 unsigned int addr_32_51 : 21;
185 unsigned int no_execute : 1;
[33be9ac]186} __attribute__ ((packed)) pte_t;
187
[7a0359b]188NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
[db3341e]189{
190 pte_t *p = &pt[i];
191
[c03ee1c]192 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
193 (!p->present) << PAGE_PRESENT_SHIFT |
194 p->uaccessible << PAGE_USER_SHIFT |
195 1 << PAGE_READ_SHIFT |
196 p->writeable << PAGE_WRITE_SHIFT |
197 (!p->no_execute) << PAGE_EXEC_SHIFT |
198 p->global << PAGE_GLOBAL_SHIFT);
[db3341e]199}
200
[7a0359b]201NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
[db3341e]202{
203 pte_t *p = &pt[i];
[a1f60f3]204
[dc0b964]205 p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
[db3341e]206 p->addr_32_51 = a >> 32;
207}
208
[7a0359b]209NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
[db3341e]210{
211 pte_t *p = &pt[i];
212
213 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
214 p->present = !(flags & PAGE_NOT_PRESENT);
215 p->uaccessible = (flags & PAGE_USER) != 0;
216 p->writeable = (flags & PAGE_WRITE) != 0;
217 p->no_execute = (flags & PAGE_EXEC) == 0;
[bfb87df]218 p->global = (flags & PAGE_GLOBAL) != 0;
[0882a9a]219
220 /*
221 * Ensure that there is at least one bit set even if the present bit is cleared.
222 */
223 p->soft_valid = 1;
[db3341e]224}
225
[1141c1a]226extern void page_arch_init(void);
[214ec25c]227extern void page_fault(unsigned int, istate_t *);
[1141c1a]228
[d1f8a87]229#endif /* __ASM__ */
230
[1141c1a]231#endif
[b45c443]232
[7f1c620]233/** @}
[b45c443]234 */
Note: See TracBrowser for help on using the repository browser.