Changeset c03ee1c in mainline for kernel/arch/amd64/include/mm/page.h


Ignore:
Timestamp:
2007-06-13T17:49:57Z (18 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
de7663f
Parents:
6b781c0
Message:

Improve comments for arch-specific implementations of hierarchical
4-level page tables. Improve formatting.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/include/mm/page.h

    r6b781c0 rc03ee1c  
    7070}
    7171
    72 #       define KA2PA(x)      ka2pa((uintptr_t)x)
    73 #       define PA2KA_CODE(x)      (((uintptr_t) (x)) + 0xffffffff80000000)
    74 #       define PA2KA(x)      (((uintptr_t) (x)) + 0xffff800000000000)
     72#       define KA2PA(x)         ka2pa((uintptr_t) x)
     73#       define PA2KA_CODE(x)    (((uintptr_t) (x)) + 0xffffffff80000000)
     74#       define PA2KA(x)         (((uintptr_t) (x)) + 0xffff800000000000)
    7575#else
    76 #       define KA2PA(x)      ((x) - 0xffffffff80000000)
    77 #       define PA2KA(x)      ((x) + 0xffffffff80000000)
     76#       define KA2PA(x)         ((x) - 0xffffffff80000000)
     77#       define PA2KA(x)         ((x) + 0xffffffff80000000)
    7878#endif
    7979
     80/* Number of entries in each level. */
    8081#define PTL0_ENTRIES_ARCH       512
    8182#define PTL1_ENTRIES_ARCH       512
    … …  
    8384#define PTL3_ENTRIES_ARCH       512
    8485
    85 #define PTL0_SIZE_ARCH       ONE_FRAME
    86 #define PTL1_SIZE_ARCH       ONE_FRAME
    87 #define PTL2_SIZE_ARCH       ONE_FRAME
    88 #define PTL3_SIZE_ARCH       ONE_FRAME
    89 
    90 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr)>>39)&0x1ff)
    91 #define PTL1_INDEX_ARCH(vaddr)  (((vaddr)>>30)&0x1ff)
    92 #define PTL2_INDEX_ARCH(vaddr)  (((vaddr)>>21)&0x1ff)
    93 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>12)&0x1ff)
    94 
    95 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
    96 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
    97 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
    98 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((uintptr_t *) ((((uint64_t) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
    99 
    100 #define SET_PTL0_ADDRESS_ARCH(ptl0)             (write_cr3((uintptr_t) (ptl0)))
    101 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
    102 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)       set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
    103 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)       set_pt_addr((pte_t *)(ptl2), (index_t)(i), a)
    104 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      set_pt_addr((pte_t *)(ptl3), (index_t)(i), a)
    105 
    106 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
    107 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            get_pt_flags((pte_t *)(ptl1), (index_t)(i))
    108 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            get_pt_flags((pte_t *)(ptl2), (index_t)(i))
    109 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *)(ptl3), (index_t)(i))
    110 
    111 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
    112 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)         set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x))
    113 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)         set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x))
    114 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
    115 
    116 #define PTE_VALID_ARCH(p)                       (*((uint64_t *) (p)) != 0)
    117 #define PTE_PRESENT_ARCH(p)                     ((p)->present != 0)
    118 #define PTE_GET_FRAME_ARCH(p)                   ((((uintptr_t)(p)->addr_12_31)<<12) | ((uintptr_t)(p)->addr_32_51<<32))
    119 #define PTE_WRITABLE_ARCH(p)                    ((p)->writeable != 0)
    120 #define PTE_EXECUTABLE_ARCH(p)                  ((p)->no_execute == 0)
     86/* Page table sizes for each level. */
     87#define PTL0_SIZE_ARCH          ONE_FRAME
     88#define PTL1_SIZE_ARCH          ONE_FRAME
     89#define PTL2_SIZE_ARCH          ONE_FRAME
     90#define PTL3_SIZE_ARCH          ONE_FRAME
     91
     92/* Macros calculating indices into page tables in each level. */
     93#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ff)
     94#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ff)
     95#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ff)
     96#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ff)
     97
     98/* Get PTE address accessors for each level. */
     99#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     100        ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \
     101            (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32)))
     102#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     103        ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \
     104            (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32)))
     105#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     106        ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \
     107            (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32)))
     108#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     109        ((uintptr_t *) \
     110            ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \
     111            (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32)))
     112
     113/* Set PTE address accessors for each level. */
     114#define SET_PTL0_ADDRESS_ARCH(ptl0) \
     115        (write_cr3((uintptr_t) (ptl0)))
     116#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     117        set_pt_addr((pte_t *) (ptl0), (index_t) (i), a)
     118#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
     119        set_pt_addr((pte_t *) (ptl1), (index_t) (i), a)
     120#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
     121        set_pt_addr((pte_t *) (ptl2), (index_t) (i), a)
     122#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     123        set_pt_addr((pte_t *) (ptl3), (index_t) (i), a)
     124
     125/* Get PTE flags accessors for each level. */
     126#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     127        get_pt_flags((pte_t *) (ptl0), (index_t) (i))
     128#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     129        get_pt_flags((pte_t *) (ptl1), (index_t) (i))
     130#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     131        get_pt_flags((pte_t *) (ptl2), (index_t) (i))
     132#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     133        get_pt_flags((pte_t *) (ptl3), (index_t) (i))
     134
     135/* Set PTE flags accessors for each level. */
     136#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     137        set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
     138#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
     139        set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x))
     140#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
     141        set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x))
     142#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     143        set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
     144
     145/* Macros for querying the last-level PTE entries. */
     146#define PTE_VALID_ARCH(p) \
     147        (*((uint64_t *) (p)) != 0)
     148#define PTE_PRESENT_ARCH(p) \
     149        ((p)->present != 0)
     150#define PTE_GET_FRAME_ARCH(p) \
     151        ((((uintptr_t) (p)->addr_12_31) << 12) | \
     152            ((uintptr_t) (p)->addr_32_51 << 32))
     153#define PTE_WRITABLE_ARCH(p) \
     154        ((p)->writeable != 0)
     155#define PTE_EXECUTABLE_ARCH(p) \
     156        ((p)->no_execute == 0)
    121157
    122158#ifndef __ASM__
    … …  
    124160/* Page fault error codes. */
    125161
    126 /** When bit on this position is 0, the page fault was caused by a not-present page. */
    127 #define PFERR_CODE_P            (1<<0) 
     162/** When bit on this position is 0, the page fault was caused by a not-present
     163 * page.
     164 */
     165#define PFERR_CODE_P            (1 << 0) 
    128166
    129167/** When bit on this position is 1, the page fault was caused by a write. */
    130 #define PFERR_CODE_RW           (1<<1)
     168#define PFERR_CODE_RW           (1 << 1)
    131169
    132170/** When bit on this position is 1, the page fault was caused in user mode. */
    133 #define PFERR_CODE_US           (1<<2)
     171#define PFERR_CODE_US           (1 << 2)
    134172
    135173/** When bit on this position is 1, a reserved bit was set in page directory. */
    136 #define PFERR_CODE_RSVD         (1<<3)
    137 
    138 /** When bit on this position os 1, the page fault was caused during instruction fecth. */
    139 #define PFERR_CODE_ID           (1<<4)
     174#define PFERR_CODE_RSVD         (1 << 3)
     175
     176/** When bit on this position os 1, the page fault was caused during instruction
     177 * fecth.
     178 */
     179#define PFERR_CODE_ID           (1 << 4)
    140180
    141181static inline int get_pt_flags(pte_t *pt, index_t i)
    … …  
    143183        pte_t *p = &pt[i];
    144184       
    145         return (
    146                 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
    147                 (!p->present)<<PAGE_PRESENT_SHIFT |
    148                 p->uaccessible<<PAGE_USER_SHIFT |
    149                 1<<PAGE_READ_SHIFT |
    150                 p->writeable<<PAGE_WRITE_SHIFT |
    151                 (!p->no_execute)<<PAGE_EXEC_SHIFT |
    152                 p->global<<PAGE_GLOBAL_SHIFT
    153         );
     185        return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
     186            (!p->present) << PAGE_PRESENT_SHIFT |
     187            p->uaccessible << PAGE_USER_SHIFT |
     188            1 << PAGE_READ_SHIFT |
     189            p->writeable << PAGE_WRITE_SHIFT |
     190            (!p->no_execute) << PAGE_EXEC_SHIFT |
     191            p->global << PAGE_GLOBAL_SHIFT);
    154192}
    155193
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